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| data sheet v1.3 2011-07 microcontrollers 16/32-bit architecture xc2288h, xc2289h 16/32-bit single-chip microcontroller with 32-bit performance xc2000 family / high line
edition 2011-07 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet v1.3 2011-07 microcontrollers 16/32-bit architecture xc2288h, xc2289h 16/32-bit single-chip microcontroller with 32-bit performance xc2000 family / high line xc2288h, xc2289h xc2000 family / high line data sheet 4 v1.3, 2011-07 trademarks c166?, tricore? and dave? are trademarks of infineon technologies ag. xc228xh data sheet revision history: v1.3 2011-07 previous versions: v1.2, 2010-09 v1.1, 2010-02 preliminary page subjects (major changes since last revision) 11 clarified available flash and sram memory allocation. 77 usic ?qspi? protocol shortcut remov ed due to ambiguity (interpreted as queued spi or quad spi). 108 relaxed the conditions for short-term deviation of internal clock source frequency f int . 108 added startup time from power-on t spo 112 removed the 128mhz conditions for n wsfle 119 added the minimum pll free running frequency. reduced the min/max bandwidth. 139 added notes on required pad settings for flexray operation. added note on flexray operation frequency. 139 corrected parameter name f(oscdd) to f(osc) in fleyray timing table. 147 thermal resistance values updated. we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuousl y improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com xc2288h, xc2289h xc2000 family / high line table of contents data sheet 5 v1.3, 2011-07 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 basic device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 special device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 definition of feature variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1 memory subsystem and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5 memory checker module (mchk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.6 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.8 capture/compare units (cc1 and cc2) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.9 capture/compare units ccu6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.10 general purpose timer (gpt12e) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.11 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.12 a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.13 universal serial interface channel modules (usic) . . . . . . . . . . . . . . . . . 76 3.14 multican module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.15 flexray? protocol controller (e-ray) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.16 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.17 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.18 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.19 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.20 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.21 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2 voltage range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.1 parameter interpretati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.3 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.1 dc parameters for upper voltage area . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2 dc parameters for lower voltage area . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.4 analog/digital converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table of contents xc2288h, xc2289h xc2000 family / high line table of contents data sheet 6 v1.3, 2011-07 4.5 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.6 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.7 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.7.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.7.2 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.7.2.1 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.7.2.2 wakeup clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.7.2.3 selecting and changing the operating frequency . . . . . . . . . . . . . 120 4.7.3 external clock input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.7.4 pad properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.7.5 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.7.5.1 bus cycle control with the ready input . . . . . . . . . . . . . . . . . . . . 132 4.7.6 synchronous serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.7.7 flexray interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.7.8 debug interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.2 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 xc2288h, xc2289h xc2000 family / high line summary of features data sheet 7 v1.3, 2011-07 16/32-bit single-chip microcontroller with 32-bit performance xc228xh (xc2000 family) 1 summary of features for a quick overview and easy reference, the features of the xc228xh are summarized here. ? high-performance cpu with five-stage pipeline and mpu ? 10 ns instruction cycle @ 100 mhz cpu clock (single-cycle execution) ? one-cycle 32-bit addition and subtraction with 40-bit result ? one-cycle multiplication (16 xc2288h, xc2289h xc2000 family / high line summary of features data sheet 8 v1.3, 2011-07 ? on-chip peripheral modules ? two synchronizable a/d converters with up to 24 channels, 10-bit resolution, conversion time below 1 xc2288h, xc2289h xc2000 family / high line summary of features data sheet 9 v1.3, 2011-07 ordering information the ordering code for an infineon microcontroller provides an exact reference to a specific product. this ordering code identifies: ? the derivative itself, i.e. its function se t, the temperature range, and the supply voltage ? the temperature range: ? saf-?: -40c to 85c ? sah-?: -40c to 110c ? sak-?: -40c to 125c ? the package and the type of delivery. for ordering codes for the xc228xh please contact your sales representative or local distributor. this document describes several derivatives of the xc228xh group: basic device types are readily available and special device types are only available on request. as this document refers to all of these deri vatives, some descriptions may not apply to a specific product, in particular to the special device types. for simplicity the term xc228xh is used for all derivatives throughout this document. xc2288h, xc2289h xc2000 family / high line summary of features data sheet 10 v1.3, 2011-07 1.1 basic device types basic device types are available and can be ordered through infineon?s direct and/or distribution channels. 1.2 special device types special device types are only available for high-volume applications on request. table 1 synopsis of xc228xh basic device types derivative 1) 1) x is a placeholder for available s peed grade in mhz. can be 100 only. flash memory 2) 2) specific information about the on-chip flash memory in table 3 and table 4 . psram 3) 3) all derivatives additionally provide 8 kbytes sbram, 2 kbytes dpram, and 24 kbytes dsram. capt./comp. modules adc 4) chan. 4) specific information about the available channels in table 5 . analog input channels are listed for each analog/digital converter module separately (adc0 + adc1). interfaces 4) xc2288h-200fxl 1,600 kbytes 112 kbytes cc1/2 ccu60/1/2/3 16 + 8 4 can nodes, 10 serial chan. table 2 synopsis of xc228xh special device types derivative 1) 1) x is a placeholder for available s peed grade in mhz. can be 80 or 100. flash memory 2) 2) specific information about the on-chip flash memory in table 3 and table 4 . psram 3) 3) all derivatives additionally provide 8 kbytes sbram, 2 kbytes dpram, and 24 kbytes dsram. capt./comp. modules adc 4) chan. 4) specific information about the available channels in table 5 . analog input channels are listed for each analog/digital converter module separately (adc0 + adc1). interfaces 4) xc2288h-136fxl 1,088 kbytes 80 kbytes cc1/2 ccu60/1/2/3 16 + 8 4 can nodes 10 serial chan. XC2289H-136FXL 1,088 kbytes 80 kbytes cc1/2 ccu60/1/2/3 16 + 8 2 flexray nodes 6 can nodes 10 serial chan. xc2289h-200fxl 1,600 kbytes 112 kbytes cc1/2 ccu60/1/2/3 16 + 8 2 flexray nodes 6 can nodes 10 serial chan. xc2288h, xc2289h xc2000 family / high line summary of features data sheet 11 v1.3, 2011-07 1.3 definition of feature variants the xc228xh types are offered with several flash memory sizes. table 3 and table 4 describe the location of the available flash memory. the xc228xh types are offered wit h different interface options. table 5 lists the available channels for each option. table 3 continuous flash memory ranges total flash size 1st range 1) 1) the uppermost 4-kbyte sector of the first flash segment is reserved for internal use (c0?f000 h to c0?ffff h ). 2nd range 3rd range 1,600 kbytes c0?0000 h table 4 flash memory module allocation (in kbytes) total flash size flash 0 1) 1) the uppermost 4-kbyte sector of the first flash segment is reserved for internal use (c0?f000 h to c0?ffff h ). flash 1 flash 2 flash 3 flash 4 flash 5 flash 6 1,600 256 255 256 256 256 256 64 1,088 256 255 256 256 - - 64 table 5 interface channel association total number available channels / message objects 16 adc0 channels ch0 xc2288h, xc2289h xc2000 family / high line summary of features data sheet 12 v1.3, 2011-07 the xc228xh types are offered wit h several psram memory sizes. figure 1 shows the allocation rules. for example 80 kbytes of psram will be allocated at e0?0000h- e1?3fffh. figure 1 psram allocation m c_xc _psram _ al l ocati on available psram reserved for psram e0'0000h (e8'0000h) e7'ffffh (ef'ffffh ) xc2288h, xc2289h xc2000 family / high line general device information data sheet 13 v1.3, 2011-07 2 general device information the xc228xh series (16/32-bit single-chip microcontroller with 32-bit performance) is a part of the in fineon xc2000 family of full-feature single- chip cmos microcontrollers. these devices extend the functionality and performance of the c166 family in terms of instructions (mac unit), peripherals, and speed. they combine high cpu performance (up to 100 million instructions per second) with extended peripheral functionality and enhanc ed io capabilities. optimized peripherals can be adapted flexibly to meet the applicat ion requirements. these derivatives utilize clock generation via pll and internal or external clock sources. on-chip memory modules include program flash, program ram, and data ram. figure 2 logic symbol mc_he_ logsymb 144 port 0 8 bit port 1 8 bit port 2 14 bit port 3 8 bit port 4 8 bit port 6 4 bit port 7 5 bit port 8 6 bit dap/jtag 2 / 4 bit trst debug 2 bit xtal1 xtal2 esr0 esr1 esr2 port 11 6 bit port 10 16 bit port 9 8 bit port 15 8 bit port 5 16 bit testm porst via port pins v agnd (1) v aref (2) v ddp (9) v ss (4) v ddi1 (4) v ddim (1) xc2288h, xc2289h xc2000 family / high line general device information data sheet 14 v1.3, 2011-07 2.1 pin configuration and definition the pins of the xc228xh are described in detail in table 6 , which includes all alternate functions. for further explanat ions please refer to the footnotes at the end of the table. the following figure summarizes all pins, show ing their locations on the four sides of the package. figure 3 xc228xh pin configuration (top view) mc_he_pin144 v ss v ddpb p0.0 p4.5 p4.6 p2.7 p5.2 p5.1 p5.0 v agnd v aref 0 v aref 1 p15.5 p15.4 p15.3 p15.2 p15.1 p15.0 p6.2 p6.1 p6.0 v ddim v ddi 1 p8.1 p7.4 p7.1 p8.2 p7.3 p7.0 p8.3 p7.2 testm v ddpb v ss v ddpa p6.3 p15.7 p15.6 v ddpb p5.3 p2.8 p0.1 p4.7 p2.9 p0.2 p10. 0 p3.0 p10. 1 p0.3 p3.1 p10. 2 p0.4 v ddi1 p2.13 p3.2 p2.10 p10. 3 p0.5 p3.3 p10. 4 p3.4 p10. 5 p3.5 p0.6 p10. 6 p3.6 p10. 7 p0.7 p3.7 v ddpb v ddpb p8 .5 p8 .6 esr 0 esr 2 esr1 porst xtal1 xta l2 p1.7 p9 .7 p1 .6 p9 .6 p1 .5 p1 0.15 p1 .4 p1 0.14 v ddi1 p9.5 p9.4 p1 .3 p1 0.13 p9 .3 p1 0.12 p1 .2 p9 .2 p1 0.11 p1 0.10 p1 .1 p1 0.9 p9 .1 p1 0.8 p9 .0 p1 .0 v ddpb v ss p2.1 v ss v ddpb p5.4 p5.5 p5 .6 p5 .7 p5.8 p5.9 p5 .1 0 p5 .1 1 p5 .1 2 p5 .1 3 p5 .1 4 p5 .1 5 p2 .1 2 p2 .1 1 p1 1.5 v dd i 1 p2.0 p1 1.4 p2.2 p1 1.3 p4.0 p2.3 p1 1.2 p4.1 p2.4 p1 1.1 p1 1.0 p2.5 p4.2 p2.6 p4.4 p4.3 v dd p b lqfp-144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 p8.4 trst xc2288h, xc2289h xc2000 family / high line general device information data sheet 15 v1.3, 2011-07 key to pin definitions ? ctrl. : the output signal for a port pin is selected by bit field pc in the associated register px_iocry. output o0 is selected by setting the respective bit field pc to 1x00 b , output o1 is selected by 1x01 b , etc. output signal oh is controlled by hardware. ? type : indicates the pad type and its power supply domain (a, b, m, 1). ? st: standard pad ? sp: special pad e.g. xtalx ? dp: double pad - can be used as standard or high speed pad ? in: input only pad ? ps: power supply pad table 6 pin definitions and functions pin symbol ctrl. type function 3 testm iin/b testmode enable enables factory test mode s, must be held high for normal operation (connect to v ddpb ). an internal pull-up device will hold this pin high when nothing is driving it. 4 p7.2 o0 / i st/b bit 2 of port 7, general purpose input/output emux0 o1 st/b external analog mux co ntrol output 0 (adc1) txdc4 o2 st/b can node 4 transmit data output txdc5 o3 st/b can node 5 transmit data output ccu62_ccp os0a ist/b ccu62 position input 0 tdi_c ih st/b jtag test data input if jtag pos. c is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. xc2288h, xc2289h xc2000 family / high line general device information data sheet 16 v1.3, 2011-07 5 p8.4 o0 / i st/b bit 4 of port 8, general purpose input/output ccu60_cou t61 o1 st/b ccu60 channel 1 output ccu62_cc6 1 o2 st/b ccu62 channel 1 output cc1_cc2 o3 st/b cc1 channel 2 output tms_d ih st/b jtag test mode selection input if jtag pos. d is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. ccu62_cc6 1inb ist/b ccu62 channel 1 input u4c1_dx1a i st/b usic4 channel 1 shift clock input 6trst iin/b test-system reset input for normal system operation, pin trst should be held low. a high level at this pin at the rising edge of porst activates the xc228xh?s debug system. in this case, pin trst must be driven low once to reset the debug system. an internal pull-down device will hold this pin low when nothing is driving it. 7 p8.3 o0 / i st/b bit 3 of port 8, general purpose input/output ccu60_cou t60 o1 st/b ccu60 channel 0 output ccu62_cc6 0 o2 st/b ccu62 channel 0 output u4c1_selo 0 o3 st/b usic4 channel 1 select/control 0 output tdi_d ih st/b jtag test data input if jtag pos. d is selected during start-up, an internal pull-up device will hold this pin low when nothing is driving it. ccu62_cc6 0inb ist/b ccu62 channel 0 input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 17 v1.3, 2011-07 8 p7.0 o0 / i st/b bit 0 of port 7, general purpose input/output t3out o1 st/b gpt12e timer t3 toggle latch output t6out o2 st/b gpt12e timer t6 toggle latch output tdo_a oh / ih st/b jtag test data output / dap1 input/output if dap pos. 0 or 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. esr2_1 i st/b esr2 trigger input 1 rxdc4b i st/b can node 4 receive data input u4c1_dx0c i st/b usic4 channel 0 receive data input 9 p7.3 o0 / i st/b bit 3 of port 7, general purpose input/output emux1 o1 st/b external analog mux co ntrol output 1 (adc1) u0c1_dout o2 st/b usic0 channel 1 shift data output u0c0_dout o3 st/b usic0 channel 0 shift data output ccu62_ccp os1a ist/b ccu62 position input 1 tms_c ih st/b jtag test mode selection input if jtag pos. c is selected during start-up, an internal pull-up device will hold this pin low when nothing is driving it. u0c1_dx0f i st/b usic0 channel 1 shift data input 10 p8.2 o0 / i st/b bit 2 of port 8, general purpose input/output ccu60_cc6 2 o1 st/b ccu60 channel 2 output txdc1 o2 st/b can node 1 transmit data output u1c1_dout o3 st/b usic1 channel 1 shift data output ccu60_cc6 2inb ist/b ccu60 channel 2 input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 18 v1.3, 2011-07 11 p7.1 o0 / i st/b bit 1 of port 7, general purpose input/output extclk o1 st/b programmable clock signal output txdc4 o2 st/b can node 4 transmit data output u4c1_dout o3 st/b usic4 channel 1 shift data output u4c1_dx0d i st/b usic4 channel 1 shift data input ccu62_ctr apa ist/b ccu62 emergency trap input brkin_c ist/b ocds break signal input 12 p7.4 o0 / i st/b bit 4 of port 7, general purpose input/output emux2 o1 st/b external analog mux co ntrol output 2 (adc1) u0c1_dout o2 st/b usic0 channel 1 shift data output u0c1_sclk out o3 st/b usic0 channel 1 shift clock output ccu62_ccp os2a ist/b ccu62 position input 2 tck_c ih st/b dap0/jtag clock input if jtag pos. c is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. if dap pos. 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. u0c0_dx0d i st/b usic0 channel 0 shift data input u0c1_dx1e i st/b usic0 channel 1 shift clock input 13 p8.1 o0 / i st/b bit 1 of port 8, general purpose input/output ccu60_cc6 1 o1 st/b ccu60 channel 1 output cc1_cc1 o2 st/b cc1 channel 1 output u4c1_mclk out o3 st/b usic4 channel 1 master clock output ccu60_cc6 1inb ist/b ccu60 channel 1 input rxdc1f i st/b can node 1 receive data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 19 v1.3, 2011-07 16 p6.0 o0 / i da/a bit 0 of port 6, general purpose input/output emux0 o1 da/a external analog mux co ntrol output 0 (adc0) txdc2 o2 da/a can node 2 transmit data output brkout o3 da/a ocds break signal output adcx_reqg tyg ida/a external request ga te input for adc0/1 u1c1_dx0e i da/a usic1 channel 1 shift data input 17 p6.1 o0 / i da/a bit 1 of port 6, general purpose input/output emux1 o1 da/a external analog mux co ntrol output 1 (adc0) t3out o2 da/a gpt12e timer t3 toggle latch output u1c1_dout o3 da/a usic1 channel 1 shift data output adcx_reqt rye ida/a external request trig ger input for adc0/1 rxdc2e i da/a can node 2 receive data input esr1_6 i da/a esr1 trigger input 6 18 p6.2 o0 / i da/a bit 2 of port 6, general purpose input/output emux2 o1 da/a external analog mux co ntrol output 2 (adc0) t6out o2 da/a gpt12e timer t6 toggle latch output u1c1_sclk out o3 da/a usic1 channel 1 shift clock output u1c1_dx1c i da/a usic1 channel 1 shift clock input 19 p6.3 o0 / i da/a bit 3 of port 6, general purpose input/output t3out o2 da/a gpt12e timer t3 toggle latch output u1c1_selo 0 o3 da/a usic1 channel 1 select/control 0 output u1c1_dx2d i da/a usic1 channel 1 shift control input adcx_reqt ryf ida/a external request trig ger input for adc0/1 21 p15.0 i in/a bit 0 of port 15, general purpose input adc1_ch0 i in/a analog input ch annel 0 for adc1 22 p15.1 i in/a bit 1 of port 15, general purpose input adc1_ch1 i in/a analog input ch annel 1 for adc1 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 20 v1.3, 2011-07 23 p15.2 i in/a bit 2 of port 15, general purpose input adc1_ch2 i in/a analog input ch annel 2 for adc1 t5ina i in/a gpt12e timer t5 count/gate input 24 p15.3 i in/a bit 3 of port 15, general purpose input adc1_ch3 i in/a analog input ch annel 3 for adc1 t5euda i in/a gpt12e timer t5 external up/down control input 25 p15.4 i in/a bit 4 of port 15, general purpose input adc1_ch4 i in/a analog input ch annel 4 for adc1 t6ina i in/a gpt12e timer t6 count/gate input 26 p15.5 i in/a bit 5 of port 15, general purpose input adc1_ch5 i in/a analog input ch annel 5 for adc1 t6euda i in/a gpt12e timer t6 external up/down control input 27 p15.6 i in/a bit 6 of port 15, general purpose input adc1_ch6 i in/a analog input ch annel 6 for adc1 28 p15.7 i in/a bit 7 of port 15, general purpose input adc1_ch7 i in/a analog input ch annel 7 for adc1 29 v aref1 - ps/a reference voltage for a/d converter adc1 30 v aref0 - ps/a reference voltage for a/d converter adc0 31 v agnd - ps/a reference ground for a/d converters adc0/1 32 p5.0 i in/a bit 0 of port 5, general purpose input adc0_ch0 i in/a analog input ch annel 0 for adc0 33 p5.1 i in/a bit 1 of port 5, general purpose input adc0_ch1 i in/a analog input ch annel 1 for adc0 34 p5.2 i in/a bit 2 of port 5, general purpose input adc0_ch2 i in/a analog input ch annel 2 for adc0 tdi_a i in/a jtag test data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 21 v1.3, 2011-07 35 p5.3 i in/a bit 3 of port 5, general purpose input adc0_ch3 i in/a analog input ch annel 3 for adc0 t3ina i in/a gpt12e timer t3 count/gate input 39 p5.4 i in/a bit 4 of port 5, general purpose input adc0_ch4 i in/a analog input ch annel 4 for adc0 ccu63_t12 hrb iin/a external run control input for t12 of ccu63 t3euda i in/a gpt12e timer t3 external up/down control input tms_a i in/a jtag test mode selection input 40 p5.5 i in/a bit 5 of port 5, general purpose input adc0_ch5 i in/a analog input ch annel 5 for adc0 ccu60_t12 hrb iin/a external run control input for t12 of ccu60 41 p5.6 i in/a bit 6 of port 5, general purpose input adc0_ch6 i in/a analog input ch annel 6 for adc0 42 p5.7 i in/a bit 7 of port 5, general purpose input adc0_ch7 i in/a analog input ch annel 7 for adc0 43 p5.8 i in/a bit 8 of port 5, general purpose input adc0_ch8 i in/a analog input ch annel 8 for adc0 adc1_ch8 i in/a analog input ch annel 8 for adc1 ccu6x_t12h rc iin/a external run contro l input for t12 of ccu60/1/2/3 ccu6x_t13h rc iin/a external run contro l input for t13 of ccu60/1/2/3 u2c0_dx0f i in/a usic2 channel 0 shift data input 44 p5.9 i in/a bit 9 of port 5, general purpose input adc0_ch9 i in/a analog input ch annel 9 for adc0 adc1_ch9 i in/a analog input ch annel 9 for adc1 cc2_t7in i in/a capcom2 timer t7 count input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 22 v1.3, 2011-07 45 p5.10 i in/a bit 10 of port 5, general purpose input adc0_ch10 i in/a analog input channel 10 for adc0 adc1_ch10 i in/a analog input channel 10 for adc1 brkin_a iin/a ocds break signal input u2c1_dx0f i in/a usic2 channel 1 shift data input ccu61_t13 hra iin/a external run control input for t13 of ccu61 46 p5.11 i in/a bit 11 of port 5, general purpose input adc0_ch11 i in/a analog input channel 11 for adc0 adc1_ch11 i in/a analog input channel 11 for adc1 47 p5.12 i in/a bit 12 of port 5, general purpose input adc0_ch12 i in/a analog input channel 12 for adc0 48 p5.13 i in/a bit 13 of port 5, general purpose input adc0_ch13 i in/a analog input channel 13 for adc0 ccu63_t13 hrf iin/a external run control input for t13 of ccu63 49 p5.14 i in/a bit 14 of port 5, general purpose input adc0_ch14 i in/a analog input channel 14 for adc0 cc1_t0in i st/b capcom1 timer t7 count input 50 p5.15 i in/a bit 15 of port 5, general purpose input adc0_ch15 i in/a analog input channel 15 for adc0 rxdc2f i in/a can node 2 receive data input 51 p2.12 o0 / i st/b bit 12 of port 2, general purpose input/output u0c0_selo 4 o1 st/b usic0 channel 0 select/control 4 output u0c1_selo 3 o2 st/b usic0 channel 1 select/control 3 output txdc2 o3 st/b can node 2 transmit data output ready ih st/b external bus interface ready input u4c0_dx0a i st/b usic4 channel 0 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 23 v1.3, 2011-07 52 p2.11 o0 / i st/b bit 11 of port 2, general purpose input/output u0c0_selo 2 o1 st/b usic0 channel 0 select/control 2 output u0c1_selo 2 o2 st/b usic0 channel 1 select/control 2 output u3c1_dout o3 st/b usic3 channel 1 shift data output bhe /wrh oh st/b external bus interf. high-byte control output can operate either as byte high enable (bhe ) or as write strobe for high byte (wrh ). 53 p11.5 o0 / i st/b bit 5 of port 11, general purpose input/output ccu61_cc6 0 o1 st/b ccu61 channel 0 output ccu61_cou t63 o2 st/b ccu61 channel 3 output u3c1_selo 1 o3 st/b usic3 channel 1 select/control 1 output ccu61_cc6 0inb ist/b ccu61 channel 0 input u3c1_dx2b i st/b usic3 channel 1 shift control input u4c0_dx2a i st/b usic4 channel 0 shift control input 55 p2.0 o0 / i st/b bit 0 of port 2, general purpose input/output txdc5 o1 st/b can node 5 transmit data output ccu63_cc6 0 o2 st/b ccu63 channel 0 output ad13 oh / ih st/b external bus interface address/data line 13 rxdc0c i st/b can node 0 receive data input ccu63_cc6 0inb ist/b ccu63 channel 0 input t5inb i st/b gpt12e timer t5 count/gate input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 24 v1.3, 2011-07 56 p2.1 o0 / i st/b bit 1 of port 2, general purpose input/output txdc0 o1 st/b can node 0 transmit data output ccu63_cc6 1 o2 st/b ccu63 channel 1 output ad14 oh / ih st/b external bus interface address/data line 14 rxdc5c i st/b can node 5 receive data input ccu63_cc6 1inb ist/b ccu63 channel 1 input t5eudb i st/b gpt12e timer t5 external up/down control input esr1_5 i st/b esr1 trigger input 5 57 p11.4 o0 / i st/b bit 4 of port 11, general purpose input/output ccu61_cc6 2 o1 st/b ccu61 channel 2 output u3c1_dout o2 st/b usic3 channel 1 shift data output rxdc5b i st/b can node 5 receive data input ccu61_cc6 2inb ist/b ccu61 channel 2 input u3c1_dx0b i st/b usic3 channel 1 shift data input 58 p2.2 o0 / i st/b bit 2 of port 2, general purpose input/output txdc1 o1 st/b can node 1 transmit data output ccu63_cc6 2 o2 st/b ccu63 channel 2 output ad15 oh / ih st/b external bus interface address/data line 15 ccu63_cc6 2inb ist/b ccu63 channel 2 input esr2_5 i st/b esr2 trigger input 5 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 25 v1.3, 2011-07 59 p11.3 o0 / i st/b bit 3 of port 11, general purpose input/output ccu61_cou t63 o1 st/b ccu61 channel 3 output ccu61_cou t62 o2 st/b ccu61 channel 2 output txdc5 o3 st/b can node 5 transmit data input ccu61_t13 hrf ist/b external run control input for t13 of ccu61 u4c0_dx1a i st/b usic4 channel 0 shift clock input 60 p4.0 o0 / i st/b bit 0 of port 4, general purpose input/output cc2_cc24 o3 / i st/b capcom2 cc24io capture inp./ compare out. cs0 oh st/b external bus interface chip select 0 output 61 p2.3 o0 / i st/b bit 3 of port 2, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output ccu63_cou t63 o2 st/b ccu63 channel 3 output cc2_cc16 o3 / i st/b capcom2 cc16io capture inp./ compare out. a16 oh st/b external bus interface address line 16 esr2_0 i st/b esr2 trigger input 0 u0c0_dx0e i st/b usic0 channel 0 shift data input u0c1_dx0d i st/b usic0 channel 1 shift data input rxdc0a i st/b can node 0 receive data input 62 p11.2 o0 / i st/b bit 2 of port 11, general purpose input/output ccu61_cc6 1 o1 st/b ccu61 channel 1 output u3c1_dout o2 st/b usic3 channel 1 shift data output u4c0_selo 1 o3 st/b usic4 channel 0 select/control 1 output ccu63_ccp os2a ist/b ccu63 position input 2 ccu61_cc6 1inb ist/b ccu61 channel 1 input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 26 v1.3, 2011-07 63 p4.1 o0 / i st/b bit 1 of port 4, general purpose input/output u3c0_selo 3 o1 st/b usic3 channel select/control 3 output txdc2 o2 st/b can node 2 transmit data output cc2_cc25 o3 / i st/b capcom2 cc25io capture inp./ compare out. cs1 oh st/b external bus interface chip select 1 output ccu62_ccp os0b ist/b ccu62 position input 0 t4eudb i st/b gpt12e timer t4 external up/down control input esr1_8 i st/b esr1 trigger input 8 64 p2.4 o0 / i st/b bit 4 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output txdc0 o2 st/b can node 0 transmit data output cc2_cc17 o3 / i st/b capcom2 cc17io capture inp./ compare out. a17 oh st/b external bus interface address line 17 esr1_0 i st/b esr1 trigger input 0 u0c0_dx0f i st/b usic0 channel 0 shift data input rxdc1a i st/b can node 1 receive data input 65 p11.1 o0 / i st/b bit 1 of port 11, general purpose input/output ccu61_cou t61 o1 st/b ccu61 channel 1 output txdc0 o2 st/b can node 0 transmit data output u3c1_selo 0 o3 st/b usic3 channel 1 select/control 0 output ccu63_ccp os1a ist/b ccu63 position input 1 ccu61_ctr apd ist/b ccu61 emergency trap input u3c1_dx2a i st/b usic3 channel 1 shift control input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 27 v1.3, 2011-07 66 p11.0 o0 / i st/b bit 0 of port 11, general purpose input/output ccu61_cou t60 o1 st/b ccu61 channel 0 output u3c1_sclk out o2 st/b usic3 channel 1 shift clock output u4c0_sclk out o3 st/b usic4 channel 0 shift clock output u4c0_dx1d i st/b usic4 channel 0 shift clock input ccu63_ccp os0a ist/b ccu63 position input 0 rxdc0f i st/b can node 0 receive data input u3c1_dx1a i st/b usic3 channel 1 shift clock input esr1_7 i st/b esr1 trigger input 7 67 p2.5 o0 / i st/b bit 5 of port 2, general purpose input/output u0c0_sclk out o1 st/b usic0 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output cc2_cc18 o3 / i st/b capcom2 cc18io capture inp./ compare out. a18 oh st/b external bus interface address line 18 u0c0_dx1d i st/b usic0 channel 0 shift clock input esr1_10 i st/b esr1 trigger input 10 u3c1_dx0d i st/b usic3 channel 1 shift data input 68 p4.2 o0 / i st/b bit 2 of port 4, general purpose input/output u3c0_sclk out o1 st/b usic3 channel 0 shift clock output txdc2 o2 st/b can node 2 transmit data output cc2_cc26 o3 / i st/b capcom2 cc26io capture inp./ compare out. cs2 oh st/b external bus interface chip select 2 output t2ina i st/b gpt12e timer t2 count/gate input ccu62_ccp os1b ist/b ccu62 position input 1 u3c0_dx1b i st/b usic3 channel 0 shift clock input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 28 v1.3, 2011-07 69 p2.6 o0 / i st/b bit 6 of port 2, general purpose input/output u0c0_selo 0 o1 st/b usic0 channel 0 select/control 0 output u0c1_selo 1 o2 st/b usic0 channel 1 select/control 1 output cc2_cc19 o3 / i st/b capcom2 cc19io capture inp./ compare out. a19 oh st/b external bus interface address line 19 u0c0_dx2d i st/b usic0 channel 0 shift control input rxdc0d i st/b can node 0 receive data input esr2_6 i st/b esr2 trigger input 6 70 p4.4 o0 / i st/b bit 4 of port 4, general purpose input/output u3c0_selo 2 o1 st/b usic3 channel 0 select/control 2 output cc2_cc28 o3 / i st/b capcom2 cc28io capture inp./ compare out. cs4 oh st/b external bus interface chip select 4 output clkin2 i st/b clock signal input 2 u3c0_dx2c i st/b usic3 channel 0 shift control input 71 p4.3 o0 / i st/b bit 3 of port 4, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output cc2_cc27 o3 / i st/b capcom2 cc27io capture inp./ compare out. cs3 oh st/b external bus interface chip select 3 output rxdc2a i st/b can node 2 receive data input t2euda i st/b gpt12e timer t2 external up/down control input ccu62_ccp os2b ist/b ccu62 position input 2 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 29 v1.3, 2011-07 75 p0.0 o0 / i st/b bit 0 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output ccu61_cc6 0 o3 st/b ccu61 channel 0 ioutput a0 oh st/b external bus interface address line 0 u1c0_dx0a i st/b usic1 channel 0 shift data input ccu61_cc6 0ina ist/b ccu61 channel 0 input esr1_11 i st/b esr1 trigger input 11 76 p4.5 o0 / i st/b bit 5 of port 4, general purpose input/output u3c0_dout o1 st/b usic3 channel 0 shift data output cc2_cc29 o3 / i st/b capcom2 cc29io capture inp./compare out. ccu61_ccp os0a ist/b ccu61 position input 0 u3c0_dx0b i st/b usic3 channel 0 shift data input esr2_10 i st/b esr2 trigger input 10 77 p4.6 o0 / i st/b bit 6 of port 4, general purpose input/output u3c0_dout o1 st/b usic3 channel 0 shift data output cc2_cc30 o3 / i st/b capcom2 cc30io capture inp./ compare out. t4ina i st/b gpt12e timer t4 count/gate input ccu61_ccp os1a ist/b ccu61 position input 1 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 30 v1.3, 2011-07 78 p2.7 o0 / i st/b bit 7 of port 2, general purpose input/output u0c1_selo 0 o1 st/b usic0 channel 1 select/control 0 output u0c0_selo 1 o2 st/b usic0 channel 0 select/control 1 output cc2_cc20 o3 / i st/b capcom2 cc20io capture inp./ compare out. a20 oh st/b external bus interface address line 20 u0c1_dx2c i st/b usic0 channel 1 shift control input rxdc1c i st/b can node 1 receive data input esr2_7 i st/b esr2 trigger input 7 u4c0_dx0d i st/b usic4 channel 0 shift data input 79 p0.1 o0 / i st/b bit 1 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc0 o2 st/b can node 0 transmit data output ccu61_cc6 1 o3 st/b ccu61 channel 1 output a1 oh st/b external bus interface address line 1 u1c0_dx0b i st/b usic1 channel 0 shift data input ccu61_cc6 1ina ist/b ccu61 channel 1 input u1c0_dx1a i st/b usic1 channel 0 shift clock input 80 p2.8 o0 / i dp/b bit 8 of port 2, general purpose input/output u0c1_sclk out o1 dp/b usic0 channel 1 shift clock output extclk o2 dp/b programmable clock signal output 1) cc2_cc21 o3 / i dp/b capcom2 cc21io capture inp./ compare out. a21 oh dp/b external bus interface address line 21 u0c1_dx1d i dp/b usic0 channel 1 shift clock input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 31 v1.3, 2011-07 81 p4.7 o0 / i st/b bit 7 of port 4, general purpose input/output cc2_cc31 o3 / i st/b capcom2 cc31io capture inp./ compare out. t4euda i st/b gpt12e timer t4 external up/down control input ccu61_ccp os2a ist/b ccu61 position input 2 82 p2.9 o0 / i st/b bit 9 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output cc2_cc22 o3 / i st/b capcom2 cc22io capture inp./ compare out. a22 oh st/b external bus interface address line 22 clkin1 i st/b clock signal input 1 tck_a ih st/b dap0/jtag clock input if jtag pos. a is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. if dap pos. 0 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. 83 p0.2 o0 / i st/b bit 2 of port 0, general purpose input/output u1c0_sclk out o1 st/b usic1 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output ccu61_cc6 2 o3 st/b ccu61 channel 2 output a2 oh st/b external bus interface address line 2 u1c0_dx1b i st/b usic1 channel 0 shift clock input ccu61_cc6 2ina ist/b ccu61 channel 2 input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 32 v1.3, 2011-07 84 p10.0 o0 / i st/b bit 0 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_cc6 0 o2 st/b ccu60 channel 0 output ad0 oh / ih st/b external bus interface address/data line 0 ccu60_cc6 0ina ist/b ccu60 channel 0 input esr1_2 i st/b esr1 trigger input 2 u0c0_dx0a i st/b usic0 channel 0 shift data input u0c1_dx0a i st/b usic0 channel 1 shift data input 85 p3.0 o0 / i st/b bit 0 of port 3, general purpose input/output u2c0_dout o1 st/b usic2 channel 0 shift data output esr1_1 i st/b esr1 trigger input 1 u2c0_dx0a i st/b usic2 channel 0 shift data input rxdc3b i st/b can node 3 receive data input u2c0_dx1a i st/b usic2 channel 0 shift clock input 86 p10.1 o0 / i st/b bit 1 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output ccu60_cc6 1 o2 st/b ccu60 channel 1 output ad1 oh / ih st/b external bus interface address/data line 1 ccu60_cc6 1ina ist/b ccu60 channel 1 input u0c0_dx1a i st/b usic0 channel 0 shift clock input u0c0_dx0b i st/b usic0 channel 0 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 33 v1.3, 2011-07 87 p0.3 o0 / i st/b bit 3 of port 0, general purpose input/output u1c0_selo 0 o1 st/b usic1 channel 0 select/control 0 output u1c1_selo 1 o2 st/b usic1 channel 1 select/control 1 output ccu61_cou t60 o3 st/b ccu61 channel 0 output a3 oh st/b external bus interface address line 3 u1c0_dx2a i st/b usic1 channel 0 shift control input rxdc0b i st/b can node 0 receive data input 88 p3.1 o0 / i st/b bit 1 of port 3, general purpose input/output u2c0_dout o1 st/b usic2 channel 0 shift data output txdc3 o2 st/b can node 3 transmit data output u2c0_dx0b i st/b usic2 channel 0 shift data input 89 p10.2 o0 / i st/b bit 2 of port 10, general purpose input/output u0c0_sclk out o1 st/b usic0 channel 0 shift clock output ccu60_cc6 2 o2 st/b ccu60 channel 2 output u3c0_selo 1 o3 st/b usic3 channel 0 select/control 1 output ad2 oh / ih st/b external bus interface address/data line 2 ccu60_cc6 2ina ist/b ccu60 channel 2 input u0c0_dx1b i st/b usic0 channel 0 shift clock input u3c0_dx2b i st/b usic3 channel 0 shift control input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 34 v1.3, 2011-07 90 p0.4 o0 / i st/b bit 4 of port 0, general purpose input/output u1c1_selo 0 o1 st/b usic1 channel 1 select/control 0 output u1c0_selo 1 o2 st/b usic1 channel 0 select/control 1 output ccu61_cou t61 o3 st/b ccu61 channel 1 output a4 oh st/b external bus interface address line 4 u1c1_dx2a i st/b usic1 channel 1 shift control input rxdc1b i st/b can node 1 receive data input esr2_8 i st/b esr2 trigger input 8 92 p2.13 o0 / i st/b bit 13 of port 2, general purpose input/output u2c1_selo 2 o1 st/b usic2 channel 1 select/control 2 output u4c0_dout o3 st/b usic4 channel 0 shift data output u4c0_dx0e i st/b usic4 channel 0 shift data input rxdc2d i st/b can node 2 receive data input 93 p3.2 o0 / i st/b bit 2 of port 3, general purpose input/output u2c0_sclk out o1 st/b usic2 channel 0 shift clock output txdc3 o2 st/b can node 3 transmit data output u2c0_dx1b i st/b usic2 channel 0 shift clock input 94 p2.10 o0 / i st/b bit 10 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output u0c0_selo 3 o2 st/b usic0 channel 0 select/control 3 output cc2_cc23 o3 / i st/b capcom2 cc23io capture inp./ compare out. a23 oh st/b external bus interface address line 23 u0c1_dx0e i st/b usic0 channel 1 shift data input capina i st/b gpt12e register caprel capture input u3c1_dx0a i st/b usic3 channel 1 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 35 v1.3, 2011-07 95 p10.3 o0 / i st/b bit 3 of port 10, general purpose input/output ccu60_cou t60 o2 st/b ccu60 channel 0 output ad3 oh / ih st/b external bus interface address/data line 3 u0c0_dx2a i st/b usic0 channel 0 shift control input u0c1_dx2a i st/b usic0 channel 1 shift control input u3c0_dx0a i st/b usic3 channel 0 shift data input 96 p0.5 o0 / i st/b bit 5 of port 0, general purpose input/output u1c1_sclk out o1 st/b usic1 channel 1 shift clock output u1c0_selo 2 o2 st/b usic1 channel 0 select/control 2 output ccu61_cou t62 o3 st/b ccu61 channel 2 output a5 oh st/b external bus interface address line 5 u1c1_dx1a i st/b usic1 channel 1 shift clock input u1c0_dx1c i st/b usic1 channel 0 shift clock input rxdc3e i st/b can node 3 receive data input 97 p3.3 o0 / i st/b bit 3 of port 3, general purpose input/output u2c0_selo 0 o1 st/b usic2 channel 0 select/control 0 output u2c1_selo 1 o2 st/b usic2 channel 1 select/control 1 output u4c0_selo 0 o3 st/b usic4 channel 0 select/control 0 output u2c0_dx2a i st/b usic2 channel 0 shift control input rxdc3a i st/b can node 3 receive data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 36 v1.3, 2011-07 98 p10.4 o0 / i st/b bit 4 of port 10, general purpose input/output u0c0_selo 3 o1 st/b usic0 channel 0 select/control 3 output ccu60_cou t61 o2 st/b ccu60 channel 1 output u3c0_dout o3 st/b usic3 channel 0 shift data output ad4 oh / ih st/b external bus interface address/data line 4 u0c0_dx2b i st/b usic0 channel 0 shift control input u0c1_dx2b i st/b usic0 channel 1 shift control input esr1_9 i st/b esr1 trigger input 9 99 p3.4 o0 / i st/b bit 4 of port 3, general purpose input/output u2c1_selo 0 o1 st/b usic2 channel 1 select/control 0 output u2c0_selo 1 o2 st/b usic2 channel 0 select/control 1 output u0c0_selo 4 o3 st/b usic0 channel 0 select/control 4 output u2c1_dx2a i st/b usic2 channel 1 shift control input rxdc4a i st/b can node 4 receive data input 100 p10.5 o0 / i st/b bit 5 of port 10, general purpose input/output u0c1_sclk out o1 st/b usic0 channel 1 shift clock output ccu60_cou t62 o2 st/b ccu60 channel 2 output u2c0_dout o3 st/b usic2 channel 0 shift data output ad5 oh / ih st/b external bus interface address/data line 5 u0c1_dx1b i st/b usic0 channel 1 shift clock input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 37 v1.3, 2011-07 101 p3.5 o0 / i st/b bit 5 of port 3, general purpose input/output u2c1_sclk out o1 st/b usic2 channel 1 shift clock output u2c0_selo 2 o2 st/b usic2 channel 0 select/control 2 output u0c0_selo 5 o3 st/b usic0 channel 0 select/control 5 output u2c1_dx1a i st/b usic2 channel 1 shift clock input 102 p0.6 o0 / i st/b bit 6 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output ccu61_cou t63 o3 st/b ccu61 channel 3 output a6 oh st/b external bus interface address line 6 u1c1_dx0a i st/b usic1 channel 1 shift data input ccu61_ctr apa ist/b ccu61 emergency trap input u1c1_dx1b i st/b usic1 channel 1 shift clock input 103 p10.6 o0 / i st/b bit 6 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output txdc4 o2 st/b can node 4 transmit data output u1c0_selo 0 o3 st/b usic1 channel 0 select/control 0 output ad6 oh / ih st/b external bus interface address/data line 6 u0c0_dx0c i st/b usic0 channel 0 shift data input u1c0_dx2d i st/b usic1 channel 0 shift control input ccu60_ctr apa ist/b ccu60 emergency trap input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 38 v1.3, 2011-07 104 p3.6 o0 / i st/b bit 6 of port 3, general purpose input/output u2c1_dout o1 st/b usic2 channel 1 shift data output txdc4 o2 st/b can node 4 transmit data output u0c0_selo 6 o3 st/b usic0 channel 0 select/control 6 output u2c1_dx0a i st/b usic2 channel 1 shift data input u2c1_dx1b i st/b usic2 channel 1 shift clock input 105 p10.7 o0 / i st/b bit 7 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_cou t63 o2 st/b ccu60 channel 3 output ad7 oh / ih st/b external bus interface address/data line 7 u0c1_dx0b i st/b usic0 channel 1 shift data input ccu60_ccp os0a ist/b ccu60 position input 0 rxdc4c i st/b can node 4 receive data input t4inb i st/b gpt12e timer t4 count/gate input 106 p0.7 o0 / i st/b bit 7 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output u1c0_selo 3 o2 st/b usic1 channel 0 select/control 3 output txdc3 o3 st/b can node 3 transmit data output a7 oh st/b external bus interface address line 7 u1c1_dx0b i st/b usic1 channel 1 shift data input ccu61_ctr apb ist/b ccu61 emergency trap input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 39 v1.3, 2011-07 107 p3.7 o0 / i st/b bit 7 of port 3, general purpose input/output u2c1_dout o1 st/b usic2 channel 1 shift data output u2c0_selo 3 o2 st/b usic2 channel 0 select/control 3 output u0c0_selo 7 o3 st/b usic0 channel 0 select/control 7 output u2c1_dx0b i st/b usic2 channel 1 shift data input 111 p1.0 o0 / i st/b bit 0 of port 1, general purpose input/output u1c0_mclk out o1 st/b usic1 channel 0 master clock output u1c0_selo 4 o2 st/b usic1 channel 0 select/control 4 output a8 oh st/b external bus interface address line 8 esr1_3 i st/b esr1 trigger input 3 ccu62_ctr apb ist/b ccu62 emergency trap input t6inb i st/b gpt12e timer t6 count/gate input 112 p9.0 o0 / i st/b bit 0 of port 9, general purpose input/output ccu63_cc6 0 o1 st/b ccu63 channel 0 output cc1_cc6 o2 st/b capcom1 cc6 compare output ccu63_cc6 0ina ist/b ccu63 channel 0 input t6eudb i st/b gpt12e timer t6 external up/down control input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 40 v1.3, 2011-07 113 p10.8 o0 / i st/b bit 8 of port 10, general purpose input/output u0c0_mclk out o1 st/b usic0 channel 0 master clock output u0c1_selo 0 o2 st/b usic0 channel 1 select/control 0 output u2c1_dout o3 st/b usic2 channel 1 shift data output ad8 oh / ih st/b external bus interface address/data line 8 ccu60_ccp os1a ist/b ccu60 position input 1 u0c0_dx1c i st/b usic0 channel 0 shift clock input brkin_b ist/b ocds break signal input t3eudb i st/b gpt12e timer t3 external up/down control input eray_rxda i st/b eray receive data input channel a esr2_11 i st/b esr2 trigger input 11 114 p9.1 o0 / i dp/b bit 1 of port 9, general purpose input/output ccu63_cc6 1 o1 dp/b ccu63 channel 1 output cc1_cc5 o2 dp/b capcom1 cc5 compare output eray_txdb o3 dp/b eray transmit data output channel b ccu63_cc6 1ina idp/b ccu63 channel 1 input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 41 v1.3, 2011-07 115 p10.9 o0 / i dp/b bit 9 of port 10, general purpose input/output u0c0_selo 4 o1 dp/b usic0 channel 0 select/control 4 output u0c1_mclk out o2 dp/b usic0 channel 1 master clock output eray_txda o3 dp/b eray transmit data output channel a ad9 oh / ih dp/b external bus interface address/data line 9 ccu60_ccp os2a idp/b ccu60 position input 2 tck_b ih dp/b dap0/jtag clock input if jtag pos. b is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. if dap pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. t3inb i dp/b gpt12e timer t3 count/gate input 116 p1.1 o0 / i st/b bit 1 of port 1, general purpose input/output ccu62_cou t62 o1 st/b ccu62 channel 2 output u1c0_selo 5 o2 st/b usic1 channel 0 select/control 5 output u2c1_dout o3 st/b usic2 channel 1 shift data output a9 oh st/b external bus interface address line 9 esr2_3 i st/b esr2 trigger input 3 u2c1_dx0c i st/b usic2 channel 1 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 42 v1.3, 2011-07 117 p10.10 o0 / i st/b bit 10 of port 10, general purpose input/output u0c0_selo 0 o1 st/b usic0 channel 0 select/control 0 output ccu60_cou t63 o2 st/b ccu60 channel 3 output eray_txen a o3 st/b eray transmit enable output channel a ad10 oh / ih st/b external bus interface address/data line 10 u0c0_dx2c i st/b usic0 channel 0 shift control input u0c1_dx1a i st/b usic0 channel 1 shift clock input tdi_b ih st/b jtag test data input if jtag pos. b is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. 118 p10.11 o0 / i st/b bit 11 of port 10, general purpose input/output u1c0_sclk out o1 st/b usic1 channel 0 shift clock output brkout o2 st/b ocds break signal output u3c0_selo 0 o3 st/b usic3 channel 0 select/control 0 output ad11 oh / ih st/b external bus interface address/data line 11 u1c0_dx1d i st/b usic1 channel 0 shift clock input rxdc2b i st/b can node 2 receive data input tms_b ih st/b jtag test mode selection input if jtag pos. b is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. u3c0_dx2a i st/b usic3 channel 0 shift control input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 43 v1.3, 2011-07 119 p9.2 o0 / i st/b bit 2 of port 9, general purpose input/output ccu63_cc6 2 o1 st/b ccu63 channel 2 output cc1_cc4 o2 st/b capcom1 cc4 compare output eray_txen b o3 st/b eray transmit enable output channel b ccu63_cc6 2ina ist/b ccu63 channel 2 input capinb i st/b gpt12e register caprel capture input 120 p1.2 o0 / i st/b bit 2 of port 1, general purpose input/output ccu62_cc6 2 o1 st/b ccu62 channel 2 output u1c0_selo 6 o2 st/b usic1 channel 0 select/control 6 output u2c1_sclk out o3 st/b usic2 channel 1 shift clock output a10 oh st/b external bus interface address line 10 esr1_4 i st/b esr1 trigger input 4 ccu61_t12 hrb ist/b external run control input for t12 of ccu61 ccu62_cc6 2ina ist/b ccu62 channel 2 input u2c1_dx0d i st/b usic2 channel 1 shift data input u2c1_dx1c i st/b usic2 channel 1 shift clock input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 44 v1.3, 2011-07 121 p10.12 o0 / i st/b bit 12 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc2 o2 st/b can node 2 transmit data output tdo_b oh / ih st/b jtag test data output / dap1 input/output if dap pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. ad12 oh / ih st/b external bus interface address/data line 12 u1c0_dx0c i st/b usic1 channel 0 shift data input u1c0_dx1e i st/b usic1 channel 0 shift clock input 122 p9.3 o0 / i st/b bit 3 of port 9, general purpose input/output ccu63_cou t60 o1 st/b ccu63 channel 0 output brkout o2 st/b ocds break signal output 123 p10.13 o0 / i st/b bit 13 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc3 o2 st/b can node 3 transmit data output u1c0_selo 3 o3 st/b usic1 channel 0 select/control 3 output wr /wrl oh st/b external bus interface write strobe output active for each external write access, when wr , active for ext. writes to the low byte, when wrl . u1c0_dx0d i st/b usic1 channel 0 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 45 v1.3, 2011-07 124 p1.3 o0 / i st/b bit 3 of port 1, general purpose input/output ccu62_cou t63 o1 st/b ccu62 channel 3 output u1c0_selo 7 o2 st/b usic1 channel 0 select/control 7 output u2c0_selo 4 o3 st/b usic2 channel 0 select/control 4 output a11 oh st/b external bus interface address line 11 esr2_4 i st/b esr2 trigger input 4 ccu62_t12 hrb ist/b external run control input for t12 of ccu62 125 p9.4 o0 / i st/b bit 4 of port 9, general purpose input/output ccu63_cou t61 o1 st/b ccu63 channel 1 output u2c0_dout o2 st/b usic2 channel 0 shift data output ccu62_cou t63 o3 st/b ccu62 channel 3 output 126 p9.5 o0 / i st/b bit 5 of port 9, general purpose input/output ccu63_cou t62 o1 st/b ccu63 channel 2 output u2c0_dout o2 st/b usic2 channel 0 shift data output ccu62_cou t62 o3 st/b ccu62 channel 2 output u2c0_dx0e i st/b usic2 channel 0 shift data input ccu60_ccp os2b ist/b ccu60 position input 2 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 46 v1.3, 2011-07 128 p10.14 o0 / i st/b bit 14 of port 10, general purpose input/output u1c0_selo 1 o1 st/b usic1 channel 0 select/control 1 output u0c1_dout o2 st/b usic0 channel 1 shift data output u3c0_sclk out o3 st/b usic3 channel 0 shift clock output rd oh st/b external bus interface read strobe output esr2_2 i st/b esr2 trigger input 2 u0c1_dx0c i st/b usic0 channel 1 shift data input rxdc3c i st/b can node 3 receive data input u3c0_dx1a i st/b usic3 channel 0 shift clock input 129 p1.4 o0 / i st/b bit 4 of port 1, general purpose input/output ccu62_cou t61 o1 st/b ccu62 channel 1 output u1c1_selo 4 o2 st/b usic1 channel 1 select/control 4 output u2c0_selo 5 o3 st/b usic2 channel 0 select/control 5 output a12 oh st/b external bus interface address line 12 u2c0_dx2b i st/b usic2 channel 0 shift control input rxdc5a i st/b can node 5 receive data input 130 p10.15 o0 / i st/b bit 15 of port 10, general purpose input/output u1c0_selo 2 o1 st/b usic1 channel 0 select/control 2 output u0c1_dout o2 st/b usic0 channel 1 shift data output u1c0_dout o3 st/b usic1 channel 0 shift data output ale oh st/b external bus interf. addr. latch enable output u0c1_dx1c i st/b usic0 channel 1 shift clock input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 47 v1.3, 2011-07 131 p1.5 o0 / i st/b bit 5 of port 1, general purpose input/output ccu62_cou t60 o1 st/b ccu62 channel 0 output u1c1_selo 3 o2 st/b usic1 channel 1 select/control 3 output brkout o3 st/b ocds break signal output a13 oh st/b external bus interface address line 13 u2c0_dx0c i st/b usic2 channel 0 shift data input 132 p9.6 o0 / i st/b bit 6 of port 9, general purpose input/output ccu63_cou t63 o1 st/b ccu63 channel 3 output ccu63_cou t62 o2 st/b ccu63 channel 2 output ccu62_cou t61 o3 st/b ccu62 channel 1 output ccu63 _ctrapa ist/b ccu63 emergency trap input ccu60_ccp os1b ist/b ccu60 position input 1 eray_rxdb i st/b eray receive data input channel b 133 p1.6 o0 / i st/b bit 6 of port 1, general purpose input/output ccu62_cc6 1 o1 / i st/b ccu62 channel 1 output u1c1_selo 2 o2 st/b usic1 channel 1 select/control 2 output u2c0_dout o3 st/b usic2 channel 0 shift data output a14 oh st/b external bus interface address line 14 u2c0_dx0d i st/b usic2 channel 0 shift data input ccu62_cc6 1ina ist/b ccu62 channel 1 input u4c1_dx0a i st/b usic4 channel 1 shift data input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 48 v1.3, 2011-07 134 p9.7 o0 / i st/b bit 7 of port 9, general purpose input/output ccu62_cou t60 o1 st/b ccu62 channel 0 output ccu62_cou t63 o2 st/b ccu62 channel 3 output ccu63_ctr apb ist/b ccu63 emergency trap input u2c0_dx1d i st/b usic2 channel 0 shift clock input ccu60_ccp os0b ist/b ccu60 position input 0 135 p1.7 o0 / i st/b bit 7 of port 1, general purpose input/output ccu62_cc6 0 o1 st/b ccu62 channel 0 output u1c1_mclk out o2 st/b usic1 channel 1 master clock output u2c0_sclk out o3 st/b usic2 channel 0 shift clock output a15 oh st/b external bus interface address line 15 u2c0_dx1c i st/b usic2 channel 0 shift clock input ccu62_cc6 0ina ist/b ccu62 channel 0 input rxdc4e i st/b can node 4 receive data input 136 xtal2 o sp/m crystal oscillator amplifier output 137 xtal1 i sp/m crystal oscillator amplifier input to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. voltages on xtal1 must comply to the core supply voltage v ddim . esr2_9 i st/b esr2 trigger input 9 table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 49 v1.3, 2011-07 138 porst iin/b power on reset input a low level at this pin resets the xc228xh completely. a spike filter suppresses input pulses <10 ns. input pulses >100 ns safely pass the filter. the minimum duration for a safe recognition should be 120 ns. an internal pull-up device will hold this pin high when nothing is driving it. 139 esr1 o0 / i st/b external service request 1 after power-up, an internal weak pull-up device holds this pin high when nothing is driving it. rxdc0e i st/b can node 0 receive data input u1c0_dx0f i st/b usic1 channel 0 shift data input u1c0_dx2c i st/b usic1 channel 0 shift control input u1c1_dx0c i st/b usic1 channel 1 shift data input u1c1_dx2b i st/b usic1 channel 1 shift control input u2c1_dx2c i st/b usic2 channel 1 shift control input 140 esr2 o0 / i st/b external service request 2 after power-up, an internal weak pull-up device holds this pin high when nothing is driving it. rxdc1e i st/b can node 1 receive data input ccu60_ctr apc ist/b ccu60 emergency trap input ccu61_ctr apc ist/b ccu61 emergency trap input ccu62_ctr apc ist/b ccu62 emergency trap input ccu63_ctr apc ist/b ccu63 emergency trap input u1c1_dx0d i st/b usic1 channel 1 shift data input u1c1_dx2c i st/b usic1 channel 1 shift control input u2c1_dx0e i st/b usic2 channel 1 shift data input u2c1_dx2b i st/b usic2 channel 1 shift control input table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 50 v1.3, 2011-07 141 esr0 o0 / i st/b external service request 0 after power-up, esr0 operates as open-drain bidirectional reset with a weak pull-up. u1c0_dx0e i st/b usic1 channel 0 shift data input u1c0_dx2b i st/b usic1 channel 0 shift control input 142 p8.6 o0 / i st/b bit 6 of port 8, general purpose input/output ccu60_cou t63 o1 st/b ccu60 channel 3 output cc1_cc3 o2 st/b capcom1 cc3 compare output mchk_mat ch o3 st/b memory checker match output ccu60_ctr apb ist/b ccu60 emergency trap input brkin_d ist/b ocds break signal input ccu62_ctr apd ist/b ccu62 emergency trap input u4c1_dx2a i st/b usic4 channel 1 shift control input 143 p8.5 o0 / i st/b bit 5 of port 8, general purpose input/output ccu60_cou t62 o1 st/b ccu60 channel 2 output ccu62_cc6 2 o2 st/b ccu62 channel 2 output u4c1_sclk out o3 st/b usic4 channel 1 shift clock output u4c1_dx1c i st/b usic4 channel 1 shift clock input tck_d ih st/b dap0/jtag clock input if jtag pos. d is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. ccu62_cc6 2inb ist/b ccu62 channel 2 input 15 v ddim - ps/m digital core supply voltage for domain m decouple with a ceramic capacitor, see data sheet for details. table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 51 v1.3, 2011-07 14, 54, 91, 127 v ddi1 - ps/1 digital core supply voltage for domain 1 decouple with a ceramic capacitor, see data sheet for details. all v ddi1 pins must be connected to each other. 20 v ddpa - ps/a digital pad supply vo ltage for domain a connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the a/d_converters and ports p5, p6 and p15 are fed from supply voltage v ddpa . 2, 36, 38, 72, 74, 108, 110, 144 v ddpb - ps/b digital pad supply vo ltage for domain b connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the on-chip voltage regulators and all ports except p5, p6 and p15 are fed from supply voltage v ddpb . 1, 37, 73, 109 v ss - ps/-- digital ground all v ss pins must be connected to the ground-line or ground-plane. note: also the exposed pad is connected internally to v ss . to improve the emc behavior, it is recommended to connect the exposed pad to the board ground. for thermal aspects, please refer to the data sheet. board layout examples are given in an application note. 1) to generate the reference clock output for bus timing measurement, f sys must be selected as source for extclk and p2.8 must be selected as output pin. also the high-speed clock pad must be enabled. this configuration is referred to as reference clock output signal clkout. table 6 pin definitions and functions (cont?d) pin symbol ctrl. type function xc2288h, xc2289h xc2000 family / high line general device information data sheet 52 v1.3, 2011-07 2.2 identification registers the identification regi sters describe the current versio n of the xc228xh and of its modules. table 7 xc228xh identification registers short name value address notes scu_idmanuf 1820 h 00?f07e h scu_idchip 4001 h 00?f07c h marking ees-aa or es-aa 4002 h 00?f07c h marking es+aa, es-ab or ab scu_idmem 318f h 00?f07a h scu_idprog 1313 h 00?f078 h jtag_id 0018?a083 h --- marking ees-aa or es-aa 1018?a083 h --- marking es+aa 2018?a083 h --- marking es-ab or ab xc2288h, xc2289h xc2000 family / high line functional description data sheet 53 v1.3, 2011-07 3 functional description the architecture of the xc228xh combines advantages of risc, cisc, and dsp processors with an advanced per ipheral subsystem in a well -balanced desi gn. on-chip memory blocks allow the design of co mpact systems-on-silicon with maximum performance suited for computing, control, and communication. the on-chip memory blocks (program co de memory and sram, dual-port ram, data sram) and the generic peripherals are connected to the cpu by separate high-speed buses. another bus, the lxbus, connects additional on-chip resources and external resources. this bus structure enhances overall system performance by enabling the concurrent operation of seve ral subsystems of the xc228xh. the block diagram gives an overview of the on-chip components and the advanced internal bus structure of the xc228xh. figure 4 block diagram dpram cpu pmu dmu adc0 module 8-/10- bit, 24 chan. rtc mchk interrupt & pec ebc lxbus control external bus control dsram system functions clock, reset, power control, standby ram ocds debug support interrupt bus peripheral data bus analog and digital general purpose io (gpio) ports mc_h-series_blockdiagram gpt 5 timers ccx modules 16 chan. each lxbus wdt multi can shared mos, 6 nodes e-ray 2 chan. ccu6x modules 3+1 chan. each usicx modules 2 chan. each psram flash memory imb mac unit mpu adc1 module 8-/10- bit, 24 chan. xc2288h, xc2289h xc2000 family / high line functional description data sheet 54 v1.3, 2011-07 3.1 memory subsystem and organization the memory space of the xc228xh is configured in the von neumann architecture. in this architecture all internal and extern al resources, including code memory, data memory, registers and i/o ports, are organized in the same linear address space. table 8 xc228xh memory map 1) address area start loc. end loc. area size 2) notes imb register space ff?ff00 h ff?ffff h 256 bytes reserved f0?0000 h ff?feff h < 1 mbyte minus imb registers reserved for epsram e9?c000 h ef?ffff h 400 kbytes mirrors epsram emulated psram e8?0000 h e9?bfff h up to 112 kbytes with flash timing reserved for psram e1?c000 h e7?ffff h 400 kbytes mirrors psram psram e0?0000 h e1?bfff h up to 112 kbytes program sram reserved for flash d9?0000 h df?ffff h 448 kbytes flash 6 d8?0000 h d8?ffff h 64 kbytes flash 5 d4?0000 h d7?ffff h 256 kbytes flash 4 d0?0000 h d3?ffff h 256 kbytes flash 3 cc?0000 h cf?ffff h 256 kbytes flash 2 c8?0000 h cb?ffff h 256 kbytes flash 1 c4?0000 h c7?ffff h 256 kbytes flash 0 c0?0000 h c3?ffff h 256 kbytes 3) minus res. seg. external memory area 40?0000 h bf?ffff h 8 mbytes external io area 4) 21?0000 h 3f?ffff h 1,984 kbytes reserved 20?c000 h 20?ffff h 16 kbytes usic0?3 alternate regs. 20?b000 h 20?bfff h 4 kbytes accessed via ebc multican alternate regs. 20?8000 h 20?afff h 12 kbytes accessed via ebc flexray registers 20?7000 h 20?7fff h 4 kbytes accessed via ebc reserved 20?6800 h 20?6fff h 2 kbytes usic0?4 registers 20?4000 h 20?67ff h 10 kbytes accessed via ebc multican registers 20?0000 h 20?3fff h 16 kbytes accessed via ebc external memory area 01?0000 h 1f?ffff h 1984 kbytes sfr area 00?fe00 h 00?ffff h 0.5 kbytes xc2288h, xc2289h xc2000 family / high line functional description data sheet 55 v1.3, 2011-07 this common memory space consists of 16 mbytes organized as 256 segments of 64 kbytes; each segment contains four data pages of 16 kbytes. the entire memory space can be accessed bytewise or wordwise. portions of the on-chip dpram and the register spaces (esfr/sfr) additionally are directly bit addressable. the internal data memory areas and the special function register areas (sfr and esfr) are mapped into segment 0, the system segment. the program management unit (pmu) handles all code fetches and, therefore, controls access to the program memories su ch as flash memory and psram. the data management unit (dmu) handles al l data transfers and, therefore, controls access to the dsram and the on-chip peripherals. both units (pmu and dmu) are connected to the high-speed system bus so that they can exchange data. this is required if operands are read from program memory, code or data is written to the psram, code is fetched from external memory, or data is read from or written to external resources. these in clude peripherals on the lxbus such as usic or multican. the system bus allows concurrent two-wa y communication for maximum transfer performance. up to 112 kbytes of on-c hip program sram (psram) are provided to store user code or data. the psram is accessed via the pmu and is optimized for code fetches. a section of the psram with progra mmable size can be write-protected. note: the actual size of the psram depends on the quoted device type. dualport ram (dpram) 00?f600 h 00?fdff h 2 kbytes reserved for dpram 00?f200 h 00?f5ff h 1 kbytes esfr area 00?f000 h 00?f1ff h 0.5 kbytes xsfr area 00?e000 h 00?efff h 4 kbytes data sram (dsram) 00?8000 h 00?dfff h 24 kbytes external memory area 00?0000 h 00?7fff h 32 kbytes 1) accesses to the shaded areas are reserved. in devices with external bus interface these accesses generate external bus accesses. 2) the areas marked with ? xc2288h, xc2289h xc2000 family / high line functional description data sheet 56 v1.3, 2011-07 up to 24 kbytes of on-chip data sram (dsram) are used for storage of general user data. the dsram is accessed via a separate in terface and is optimized for data access. 2 kbytes of on-chip dual-port ram (dpram) provide storage for user-defined variables, for the system stack, and for gener al purpose register banks. a register bank can consist of up to 16 word-wide (r0 to r15) and/or byte-wide (rl0, rh0, ?, rl7, rh7) general purpose registers (gprs). the upper 256 bytes of the dpram are direct ly bit addressable. when used by a gpr, any location in the dpram is bit addressable. 8 kbytes of on-chip stand-by sram (sbram) provide storage for system-relevant user data that must be preserved while the major part of the device is powered down. the sbram is accessed via a specific interface and is powered in domain m. 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space) . sfrs are word-wide registers which are used to control and monitor functions of the different on-chip units. unused sfr addresses are reserved for future members of the xc2000 family. in order to ensure upward compatibility they should either not be accessed or written with zeros. in order to meet the requirements of desi gns where more memory is required than is available on chip, up to 12 mbytes (approximately, see table 8 ) of external ram and/or rom can be connected to the microcontroller. the external bus interface also provides access to external peripherals. the on-chip flash memory stores code, constant data, and control data. the 1,600 kbytes of on-chip flash memory consist of 1 module of 64 kbytes (preferably for data storage) and 6 modules of 256 kbytes . each module is organized in 4-kbyte sectors. the uppermost 4-kbyte sector of segment 0 (located in flash module 0) is used internally to store operation contro l parameters and protection information. note: the actual size of the flash memory depends on the chosen device type. each sector can be separately write protected 1) , erased and programmed (in blocks of 128 bytes). the complete flash area can be read-protected. a user-defined password sequence temporarily unlocks protected areas. the flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing. dynamic error correction provides extremely high read data security for all read access operations. access to different flash modules can be executed in parallel. for flash parameters, please see section 4.6 . 1) to save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing. xc2288h, xc2289h xc2000 family / high line functional description data sheet 57 v1.3, 2011-07 memory content protection the contents of on-chip memories can be pr otected against soft errors (induced e.g. by radiation) by activating the parity mec hanism or the error correction code (ecc). the parity mechanism can detect a single-bit error and prevent the software from using incorrect data or executing incorrect instructions. the ecc mechanism can detect and automatically correct single-bit errors. this supports the stable operation of the system. it is strongly recommended to activate the ecc mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors. xc2288h, xc2289h xc2000 family / high line functional description data sheet 58 v1.3, 2011-07 3.2 external bus controller all external memory access operations are performed by a special on-chip external bus controller (ebc). the ebc also controls access to resources co nnected to the on-chip lxbus (multican and the usic modules). the lxbus is an internal representation of the external bus that allows access to in tegrated peripherals and modules in the same way as to external components. the ebc can be programmed either to single chip mode, when no external memory is required, or to an external bus mode with the following selections 1) : ? address bus width with a range of 0 ? 24-bit ? data bus width 8-bit or 16-bit ? bus operation multiplexed or demultiplexed the bus interface uses port 10 and port 2 for addresses and data. in the demultiplexed bus modes, the lower addresses are output separately on port 0 and port 1. the number of active segment address lines is selectable , restricting the external address space to 8 mbytes ? 64 kbytes. this is required when interface lines shall be assigned to port 2. external cs signals (address windows plus default) can be generated and output on port 4 in order to save external glue logic. external modules can be directly connected to the common address/data bus and their individual select lines. important timing characteristics of the ex ternal bus interface are programmable (with registers tconcsx/fconcsx) to allow the user to adapt it to a wide range of different types of memories and external peripherals. access to very slow memories or modules with varying access times is supported by a special ?ready? function. the active level of the control input signal is selectable. in addition, up to four independent address windows may be defined (using registers addrselx) to control access to resources with different bus characteristics. these address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. all accesses to locations not covered by these four address windows are controlled by tconcs 0/fconcs0. the currently active window can generate a chip select signal. the external bus timing is based on t he rising edge of the reference clock output clkout. the external bus protocol is compat ible with that of the standard c166 family. 1) bus modes are switched dynamically if several addr ess windows with different mode settings are used. xc2288h, xc2289h xc2000 family / high line functional description data sheet 59 v1.3, 2011-07 3.3 central processing unit (cpu) the core of the cpu consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logi c unit (alu), a 32-bit/40-bit multiply and accumulate unit (mac), a register-file providing three register banks, and dedicated sfrs. the alu features a multiply-and-div ide unit, a bit-mask generator, and a barrel shifter. figure 5 cpu block diagram dpram cpu ipip rf r0 r1 gprs r14 r15 r0 r1 gprs r14 r15 ifu injection/ exception handler adu mac mca04917_x.vsd cpucon1 cpucon2 csp ip return stack fifo branch unit prefetch unit vecseg tfr +/- idx0 idx1 qx0 qx1 qr0 qr1 dpp0 dpp1 dpp2 dpp3 spseg sp stkov stkun +/- mrw mcw msw mal +/- mah multiply unit alu division unit multiply unit bit-mask-gen. barrel-shifter +/- mdc psw mdh zeros mdl ones r0 r1 gprs r14 r15 cp wb buffer 2-stage prefetch pipeline 5-stage pipeline r0 r1 gprs r14 r15 pmu dmu dsram ebc peripherals psram flash/rom xc2288h, xc2289h xc2000 family / high line functional description data sheet 60 v1.3, 2011-07 with this hardware most xc228xh instructions are executed in a single machine cycle of 10 ns @ 100-mhz cpu clock. for example, shift and rotate instructions are always processed during one ma chine cycle, no matter how m any bits are shifted. also, multiplication and most ma c instructions execute in one cycle. all multiple-cycle instructions have been optimized so that t hey can be executed very fast; for example, a 32-/16-bit division is started within 4 cycle s while the remaining cycles are executed in the background. another pipeline optimization, the branch target prediction, eliminates the execution time of branch instru ctions if the prediction was correct. the cpu has a register context consisting of up to three register banks with 16 word- wide gprs each at its disposal. one of these register banks is physi cally allocated within the on-chip dpram area. a context pointer (cp) register determines the base address of the active register bank accessed by the cpu at any time. the number of these register bank copies is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 32 kwords is provid ed for storage of temporary data. the system stack can be allocated to any location within the address space (preferably in the on-chip ram area); it is accessed by the cpu with th e stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared with t he stack pointer value during each stack access to detect stack overflow or underflow. the high performance of the cpu hardware im plementation can be be st utilized by the programmer with the highly efficient xc228xh in struction set. this includes the following instruction classes: ? standard arithmetic instructions ? dsp-oriented arithmetic instructions ? logical instructions ? boolean bit manipulation instructions ? compare and loop control instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system contro l instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands. xc2288h, xc2289h xc2000 family / high line functional description data sheet 61 v1.3, 2011-07 3.4 memory protection unit (mpu) the xc228xh?s memory protection unit (mpu) protects user-specified memory areas from unauthorized read, write, or instruct ion fetch accesses. the mpu can protect the whole address space including the peripheral area. this completes established mechanisms such as the register securi ty mechanism or stack overrun/underrun detection. four protection levels support flexible system programming where operating system, low level drivers, and applications run on se parate levels. each protection level permits different access restri ctions for instructions and/or data. every access is checked (if the mpu is enabled) and an access violating the permission rules will be marked as invalid and leads to a protection trap. a set of protection registers for each protec tion level specifies the address ranges and the access permissions. applications requ iring more than 4 protection levels can dynamically re-program the protection registers. 3.5 memory checker module (mchk) the xc228xh?s memory checker module calculates a checksum (fractional polynomial division) on a block of data, often called cyclic redundancy code (crc). it is based on a 32-bit linear feedback shift register and may, therefore, also be used to generate pseudo-random numbers. the memory checker module is a 16-bit parallel input signature compression circuitry which enables error detection within a block of data stored in me mory, registers, or communicated e.g. via serial communication lines. it reduces the probability of error masking due to repeated error patterns by ca lculating the signature of blocks of data. the polynomial used for operation is configurable, so most of the commonly used polynomials may be used. also, the block size for generating a crc result is configurable via a local counter. an interrupt may be generated if testing the current data block reveals an error. an autonomous crc compare circuitry is included to enable redundant error detection, e.g. to enable higher safety integrity levels. the memory checker module provides enhan ced fault detection (beyond parity or ecc) for data and instructions in volatile and non volatile memories. this is especially important for the safety and reliability of embedded systems. xc2288h, xc2289h xc2000 family / high line functional description data sheet 62 v1.3, 2011-07 3.6 interrupt system the architecture of the xc228xh supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. any of thes e interrupt requests can be programmed to be serviced by the interrupt controller or by the peripheral event controller (pec). using a standard interrupt service the curr ent program execution is suspended and a branch to the interrupt vector table is perfo rmed. with the pec just one cycle is ?stolen? from the current cpu activity to perform the pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source pointer, t he destination pointer, or both. an individual pec transfer counter is implicitly decre mented for each pec service except when performing in the continuous transfer mode . when this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. pec services are particularly well suited to supporting th e transmission or recept ion of blocks of data. the xc228xh has eight pec channels, each wi th fast interrupt-driven data transfer capabilities. with a minimum interrupt response time of 7/11 1) cpu clocks, the xc228xh can react quickly to the occurrence of non-deterministic events. interrupt nodes and source selection the interrupt system provides 112 physica l nodes with separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit field. most interrupt sources are assigned to a dedicated node. a particular subset of interrupt sources shares a set of nodes. the source selection can be programmed using the interrupt source selection (issr) registers. external request unit (eru) a dedicated external request unit (eru) is provided to route and preprocess selected on-chip peripheral and external interrupt requests. the eru features 4 programmable input channels with event trigger logic (etl ) a routing matrix and 4 output gating units (ogu). the etl features rising edge, falli ng edge, or both edges event detection. the ogu combines the detected interrupt ev ents and provides filtering capabilities depending on a programmable pattern match or miss. trap processing the xc228xh provides efficient mechanisms to identify and process exceptions or error conditions that arise during run-time, the so-called ?hardware traps?. a hardware trap causes an immediate system reaction simila r to a standard interrupt service (branching 1) depending if the jump cache is used or not. xc2288h, xc2289h xc2000 family / high line functional description data sheet 63 v1.3, 2011-07 to a dedicated vector table location). the occurrence of a hardware trap is also indicated by a single bit in the trap flag register (tfr ). unless another higher-priority trap service is in progress, a hardware trap will interrupt any ongoing program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. depending on the package option up to 3 external service request (esr) pins are provided. the esr unit processes their i nput values and allows to implement user controlled trap functions (system requests sr0 and sr1). in this way reset, wakeup and power control can be efficiently realized. software interrupts are supported by the ?trap? instruction in combination with an individual trap (interrupt) number. alternatively to emulate an interrupt by software a program can trigger interrupt requests by wr iting the interrupt request (ir) bit of an interrupt control register. 3.7 on-chip debug support (ocds) the on-chip debug support system built into the xc228xh provides a broad range of debug and emulation features . user software running on the xc228xh can be debugged within the target system environment. the ocds is controlled by an external debugging device via the debug interface. this either consists of the 2-pin device access po rt (dap) or of the jtag port conforming to ieee-1149. the debug interface can be completed with an optional break interface. the debugger controls the ocds with a set of dedicated registers accessible via the debug interface (dap or jtag). in addition the ocds system can be controlled by the cpu, e.g. by a monitor program. an inject ion interface allows the execution of ocds- generated instructions by the cpu. multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. single stepping is su pported, as is the in jection of arbitrary instructions and read/write a ccess to the complete internal address space. a breakpoint trigger can be answered with a cpu halt, a mo nitor call, a data transfer, or/and the activation of an external signal. tracing of data can be obtained via the debug in terface, or via the external bus interface for increased performance. tracing of program execution is supported by the xc2000 family emulation device. with this device the dap can operate on clock rates of up to 20 mhz. the dap interface uses two interface signals, the jtag interface uses four interface signals, to communicate with external circ uitry. the debug interface can be amended with two optional break lines. xc2288h, xc2289h xc2000 family / high line functional description data sheet 64 v1.3, 2011-07 3.8 capture/compare units (cc1 and cc2) each capcom unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). the capcom unit is typically used to handle high-speed i/o tasks such as pulse and waveform generation, pulse width modulation (pwm), digital to analog (d/a) conversion, software timing, or time recording with respect to external events. two 16-bit timers with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an over flow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specif ic requirements. in addition, external count inputs allow event scheduling for the captur e/compare registers relative to external events. the capture/compare register array cont ains 16 dual purpose capture/compare registers, each of which may be individual ly allocated to either capcom timer and programmed for capture or compare function. all registers have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?captured?) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the c ontents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be tak en based on the selected compare mode. table 9 compare modes compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible xc2288h, xc2289h xc2000 family / high line functional description data sheet 65 v1.3, 2011-07 when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?captured?) into the capture/compare register in response to an external event at the port pin associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be tak en based on the compare mode selected. mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare timer overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible single event mode generates single edges or pulses; can be used with any compare mode table 9 compare modes (cont?d) compare modes function xc2288h, xc2289h xc2000 family / high line functional description data sheet 66 v1.3, 2011-07 figure 6 capcom unit block diagram timer t0/t7 sixteen 16 -bit capture/ compare registers timer t1/t8 reload reg. t1rel/t8rel t0 /t 7 input control mode control (capture or compare) t1 /t 8 input control mcb05418_p11_cc12 reload reg. t0rel/t7rel t0irq, t7irq ccxirq ccxirq t1irq, t8irq ccxirq f cc t0in/t7in t6ouf ccxio ccxio ccxio f cc t6ouf capcom1 provides channels x = 0 ? 15. (see signals ccxio and ccxirq ) external sync. start external sync. start syscon1.glccst t78con. t7rsel t78con. t8rsel t01con. t1rsel t01con. t0rsel capcom2 provides channels x = 16 ? 31. (see signals ccxio and ccxirq ) xc2288h, xc2289h xc2000 family / high line functional description data sheet 67 v1.3, 2011-07 3.9 capture/compare units ccu6x the xc228xh types feature the ccu6 0, ccu61, ccu62 and ccu63 unit(s). ccu6 is a high-resolution capture and comp are unit with application-specific modes. it provides inputs to start the timers synchr onously, an important feature in devices with several ccu6 modules. the module provides two independent timers (t12, t13), that can be used for pwm generation, especially for ac motor control. additionally, special control modes for block commutation and multi-phase machines are supported. timer 12 features ? three capture/compare channels, where each channel can be used either as a capture or as a compare channel. ? supports generation of a three-phase pwm (six outputs, individual signals for high- side and low-side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to avoid short circuits in the power stage ? concurrent update of the required t12/13 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? many interrupt request sources ? hysteresis-like control mode ? automatic start on a hw event (t 12hr, for synchronization purposes) timer 13 features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? can be synchronized to t12 ? interrupt generation at period match and compare match ? single-shot mode supported ? automatic start on a hw event (t 13hr, for synchronization purposes) additional features ? block commutation for brushless dc drives implemented ? position detection via hall sensor pattern ? automatic rotational speed measurement for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac drives ? output levels can be selected and adapted to the power stage xc2288h, xc2289h xc2000 family / high line functional description data sheet 68 v1.3, 2011-07 figure 7 ccu6 block diagram timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined. timer t13 can work in compare mode only. the multi-channel control unit generates output patterns that can be modulated by timer t12 and/or timer t13. the modulation sources can be selected and combined for signal modulation. mc_ccu6_blockdiagram .vsd channel 0 channel 1 channel 2 t12 dead- time control input / output control cc62 cout62 cc61 cout61 cc60 cout60 cout63 ctrap channel 3 t13 ccpos0 1 1 1 222 1 start compare ca p t u r e 3 multi- channel control trap control compare compa re compa re compa re 1 t rap i nput ccpos1 ccpos2 output select output select 3 hall input ccu6 module kernel f sys interrupts txhr xc2288h, xc2289h xc2000 family / high line functional description data sheet 69 v1.3, 2011-07 3.10 general purpose timer (gpt12e) unit the gpt12e unit is a very flexible multif unctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt12e unit incorporates five 16-bit timers organized in two separate modules, gpt1 and gpt2. each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module. each of the three ti mers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation: time r, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. counter mode allows timer clocking in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes each timer has one associated port pi n (txin) which serves as a gate or clock input. the maximum re solution of the timers in modul e gpt1 is 4 system clock cycles. the counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (txeud), e.g. to facilitate position tracking. in incremental interface mode the gpt1 ti mers can be directly connected to the incremental position sensor signals a and b through their respective inputs txin and txeud. direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl ) which changes its state on each timer overflow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components. it may also be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to the basic operating modes, t2 and t4 may be configured as reload or capture register for timer t3. a timer used as capture or reload register is stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at the associated input pin (txin). timer t3 is reloaded with th e contents of t2 or t4 , triggered either by an external signal or a selectable state tr ansition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be continuously generated without software intervention. xc2288h, xc2289h xc2000 family / high line functional description data sheet 70 v1.3, 2011-07 figure 8 block diagram of gpt1 mc_gpt_block1 aux. timer t2 2 n :1 t2 mode control capture u/d basic clock f gpt t3con.bps1 t3otl t3out toggle latch t2in t2eud reload core timer t3 t3 mode control t3in t3eud u/d interrupt request (t3irq) t4 mode control u/d aux. timer t4 t4eud t4in reload capture interrupt request (t4irq) interrupt request (t2irq) xc2288h, xc2289h xc2000 family / high line functional description data sheet 71 v1.3, 2011-07 with its maximum resolution of 2 system clock cycles, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programma ble prescaler or with external signals. the counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a por t pin (txeud). concatenation of the timers is supported with the output toggle latch (t6o tl) of timer t6, which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, and/or it may be output on pin t6out. the overflows/underflows of timer t6 can also be used to clock the capcom2 timers and to initiate a reload from the caprel register. the caprel register can capt ure the contents of timer t5 based on an external signal transition on the corresponding port pin (capin); timer t5 may optionally be cleared after the capture procedure. this allows the xc228xh to measure absolute time differences or to perform pulse multiplication without software overhead. the capture trigger (timer t5 to caprel ) can also be generated upon transitions of gpt1 timer t3 inputs t3in and/or t3eud. this is especially advantageous when t3 operates in incremental interface mode. xc2288h, xc2289h xc2000 family / high line functional description data sheet 72 v1.3, 2011-07 figure 9 block diagram of gpt2 mc_gpt_block 2 gpt2 timer t5 2 n :1 t5 mode control gpt2 caprel t3in/ t3eud caprel mode control t6 mode control reload clear u/d capture clear u/d t5in capin interrupt request (t5irq) interrupt request (t6irq) interrupt request (crirq) basic clock f gpt t6con.bps2 t6in gpt2 timer t6 t6otl t6out t6ouf toggle ff t6eud t5eud xc2288h, xc2289h xc2000 family / high line functional description data sheet 73 v1.3, 2011-07 3.11 real time clock the real time clock (rtc) module of the xc228xh can be clocked with a clock signal selected from internal source s or external sources (pins). the rtc basically consists of a chain of divider blocks: ? selectable 32:1 and 8:1 dividers (on - off) ? the reloadable 16-bit timer t14 ? the 32-bit rtc timer block (accessible via registers rtch and rtcl) consisting of: ? a reloadable 10-bit timer ? a reloadable 6-bit timer ? a reloadable 6-bit timer ? a reloadable 10-bit timer all timers count up. each timer can generate an interrupt request. all requests are combined to a common node request. figure 10 rtc block diagram note: the registers associated with the rtc are only affected by a power reset. cnt-register rel-register 10 bits 6 bits 6 bits 10 bits t14 mcb05568b t14-register interrupt sub node rtcint mux 32 pre run cnt int3 cnt int2 cnt int1 cnt int0 f cnt f rtc t14rel 10 bits 6 bits 6 bits 10 bits : mux 8 : refclk xc2288h, xc2289h xc2000 family / high line functional description data sheet 74 v1.3, 2011-07 the rtc module can be used for different purposes: ? system clock to determine the current time and date ? cyclic time-based interrupt, to provide a system time tick independent of cpu frequency and other resources ? 48-bit timer for long-term measurements ? alarm interrupt at a defined time xc2288h, xc2289h xc2000 family / high line functional description data sheet 75 v1.3, 2011-07 3.12 a/d converters for analog signal measurement, up to two 10-bit a/d converters (adc0, adc1) with 16 + 8 multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by both a/d converters. conversions use the successive approximation method. the sample time (to charge the capacitors) and the conversion time are programmable so that t hey can be adjusted to the external circuit. the a/d converters can also operate in 8-bi t conversion mode, further reducing the conversion time. several independent conversion result regist ers, selectable inte rrupt requests, and highly flexible conversion sequences prov ide a high degree of programmability to meet the application requirements. both modules can be synchronized to allow parallel sampling of two input channels. for applications that require more analog input channels, external analog multiplexers can be controlled automatically. for app lications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converters of the xc228xh support two types of request sources which can be triggered by several internal and external events. ? parallel requests are activated at the sa me time and then executed in a predefined sequence. ? queued requests are executed in a user-defined sequence. in addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. all requests are arbitrated according to the priority level assigned to them. data reduction features reduce the number of required cpu access operations allowing the precise evaluation of analog inputs (hig h conversion rate) even at a low cpu speed. result data can be reduced by limit checking or accumulation of results. the peripheral event controller (pec) can be used to control the a/d converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of enter ing and exiting interrupt routines for each data transfer. each a/d converter contains eight result regi sters which can be concatenated to build a result fifo. wait-f or-read mode can be ena bled for each result r egister to prevent the loss of conversion data. in order to decouple analog inputs from digital noise and to avoid input trigger noise, those pins used for analog input can be disc onnected from the digital input stages. this can be selected for each pin separately with the port x digital input disable registers. the auto-power-down feature of the a/d converters minimizes the power consumption when no conversion is in progress. broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the analog signal sources (e.g. a sensor system). xc2288h, xc2289h xc2000 family / high line functional description data sheet 76 v1.3, 2011-07 3.13 universal serial interf ace channel modules (usic) the xc228xh features the usic modules us ic0, usic1, usic2, usic3, usic4. each module provides two serial communication channels. the universal serial interface channel (usi c) module is based on a generic data shift and data storage structure which is identi cal for all supported serial communication protocols. each channel supports complete fu ll-duplex operation wit h a basic data buffer structure (one transmit buffer and two receive buffer stages). in addition, the data handling software can use fifos. the protocol part (generation of shift clock/da ta/control signals) is independent of the general part and is handled by pr otocol-specific preprocessors (ppps). the usic?s input/output lines are connected to pins by a pin routing unit. the inputs and outputs of each usic channel can be assigned to different interface pins, providing great flexibility to the application software. all assignments can be made during runtime. figure 11 general structure of a usic module the regular structure of the usic m odule brings the following advantages: ? higher flexibility through configuration wi th same look-and-feel for data management ? reduced complexity for low-level dr ivers serving different protocols ? wide range of protocols with improved performances (baud rate, buffer handling) usic_basic.vsd bus interface dbu 0 dbu 1 control 0 control 1 dsu 0 dsu 1 ppp_a ppp_b ppp_c ppp_d ppp_a ppp_b ppp_c ppp_d pin routing shell buffer & shift structure protocol preprocessors pins bus f sys fractional dividers baud rate generators xc2288h, xc2289h xc2000 family / high line functional description data sheet 77 v1.3, 2011-07 target protocols each usic channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols: ? uart (asynchronous serial channel) ? module capability: maximum baud rate = f sys / 4 ? data frame length programmable from 1 to 63 bits ? msb or lsb first ? lin support (local interconnect network) ? module capability: maximum baud rate = f sys / 16 ? checksum generation under software control ? baud rate detection possible by built-in capture event of baud rate generator ? ssc/spi (synchronous serial channel with or without data buffer) ? module capability: maximum baud rate = f sys / 2, limited by loop delay ? number of data bits programm able from 1 to 63, more with explicit stop condition ? msb or lsb first ? optional control of slave select signals ? iic (inter-ic bus) ? supports baud rates of 100 kbit/s and 400 kbit/s ? iis (inter-ic sound bus) ? module capability: maximum baud rate = f sys / 2 note: depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. please note that there may be additional delays, such as internal or external propagation delays and driver dela ys (e.g. for collision detection in uart mode, for iic, etc.). xc2288h, xc2289h xc2000 family / high line functional description data sheet 78 v1.3, 2011-07 3.14 multican module the multican module contains independently operating can nodes with full-can functionality which are able to exchange da ta and remote frames using a gateway function. transmission and reception of can frames is handled in accordance with can specification v2.0 b (active). each can nod e can receive and transmit standard frames with 11-bit identifiers as well as ex tended frames with 29-bit identifiers. all can nodes share a common set of mess age objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to set up a fifo buffer. note: the number of can nodes and messa ge objects depends on the selected device type. the message objects are organized in doubl e-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list. a powerful, command-driven list controller performs all message object list operations. figure 12 block diagram of multican module mc_ multican_ block.vsd multican module kernel interrupt control f can port control can control message object buffer can node 0 linked list control clock control address decoder can node n txdcn rxdcn txdc0 rxdc0 ... ... ... xc2288h, xc2289h xc2000 family / high line functional description data sheet 79 v1.3, 2011-07 multican features ? can functionality conforming to can specification v2.0 b active for each can node (compliant to iso 11898) ? independent can nodes ? set of independent message objects (shared by the can nodes) ? dedicated control registers for each can node ? data transfer rate up to 1 mbit/s, individually programmable for each node ? flexible and powerful message transfer control and error handling capabilities ? full-can functionality for message objects: ? can be assigned to one of the can nodes ? configurable as transmit or receive objects, or as message buffer fifo ? handle 11-bit or 29-bit id entifiers with programmable a cceptance mask for filtering ? remote monitoring mode, and frame counter for monitoring ? automatic gateway mode support ? 16 individually programmable interrupt nodes ? analyzer mode for can bus monitoring xc2288h, xc2289h xc2000 family / high line functional description data sheet 80 v1.3, 2011-07 3.15 flexray? protocol controller (e-ray) the e-ray module performs communication according to the flexray? 1) protocol specification v2.1. with maximum specified clock the bitrate can be programmed to values up to 10 mbit/s. additional bus driver (bd) hardware is required for connection to the physical layer. figure 13 shows a global view of the e-ray interface. figure 13 general block diag ram of the e-ray interface the e-ray module communicates with the external world via three i/o lines each channel. the rxdax and rxdbx lines are the receive data input signals, txda and txdb lines are the transm it output signals, and txena and txenb the transmit enable signals. 1) flexray? is a trademark of the flexray consortium. eray_overview.vsd address decoder interrupt control eray module (kernel ) channel a channel b port control external request unit stop watch trigger select stpw mt external clock output f mt f clc_eray f sc l k f pl l_ er ay f sys rxdb txdb txenb rxda txda txena xc2288h, xc2289h xc2000 family / high line functional description data sheet 81 v1.3, 2011-07 clock control, address decoding, and servic e request control are managed outside the e-ray module kernel. flexray? module features for communication on a flexray? network, individual message buffers with up to 254 data bytes are configurable. the message storage consists of a single-ported message ram that holds up to 128 message buffers . all functions concerning the handling of messages are implemented in the messa ge handler. those functions are the acceptance filtering, the transfer of messages between the two flexray? channel protocol controllers and th e message ram, maintaining the transmission schedule as well as providing message status information. the register set of the e-ray ip-module can be accessed directly by an external host via the module?s host interface. these regist ers are used to cont rol/configure/monitor the flexray? channel protocol controllers, message handler, global time unit, system universal control, frame and symbol processing, network management, service request control, and to access the message ram via input / output buffer. the e-ray ip-module supports the following features: ? conformance with flexray? protocol specification v2.1 ? data rates of up to 10 mbit/s on each channel ? up to 128 message buffers configurable ? 8 kbytes of message ram for storage of e.g. 128 message buffers with max. 48 bytes data field or up to 30 message buffers with 254 bytes data sections ? configuration of message buffers with different payload lengths possible ? one configurable receive fifo ? each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive fifo ? host access to message buffers via input and output buffer. input buffer: holds message to be transferred to the message ram output buffer: holds message read from the message ram ? filtering for slot counter, cycle counter, and channel ? maskable module service requests ? network management supported ? four service request lines ? automatic delayed read access to output command request register (obcr) if a data transfer from message ram to output shadow buffer (initiated by a previous write access to the obcr) is ongoing. ? automatic delayed read access to input co mmand request register (ibcr) if a data transfer from input shadow buffer to message ram to (ini tiated by a previous write access to the ibcr) is ongoing. ? four input buffers for building up transmission frames in parallel. ? flag indicating which input buffer is currently accessible by the host. xc2288h, xc2289h xc2000 family / high line functional description data sheet 82 v1.3, 2011-07 3.16 system timer the system timer consists of a programmable prescaler and two concatenated timers (10 bits and 6 bits). both timers can gener ate interrupt requests. the clock source can be selected and the timers can also run during power reduction modes. therefore, the system timer enables the software to maintain the current time for scheduling functions or for t he implementation of a clock. 3.17 watchdog timer the watchdog timer is one of the fail-sa fe mechanisms which have been implemented to prevent the controller from malfun ctioning for longer periods of time. the watchdog timer is always enabled after an application reset of the chip. it can be disabled and enabled at any time by exec uting the instructions diswdt and enwdt respectively. the software has to service t he watchdog timer before it overflows. if this is not the case because of a hardware or software failure, the watchdog timer overflows, generating a prewarning interrupt and then a reset request. the watchdog timer is a 16-bit timer clock ed with the system clock divided by 16,384 or 256. the watchdog timer register is set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the watchdog timer is reloaded and the prescaler is cleared. time intervals between 3.2 3.18 clock generation the clock generation unit can generate the system clock signal f sys for the xc228xh from a number of external or internal clock sources: ? external clock signals with pad voltage or core voltage levels ? external crystal or resonator using the on-chip oscillator ? on-chip clock source for oper ation without crystal/resonator ? wake-up clock (ultra-low-power) to further reduce power consumption the programmable on-chip pll with multiple prescalers generates a clock signal for maximum system performance from standard cryst als, a clock input signal, or from the on-chip clock source. see also section 4.7.2 . the oscillator watchdog (owd) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. in this ca se, the system can be supplied with an emergency clock to enable operation even after an external clock failure. all available clock signals can be output on one of two selectable pins. xc2288h, xc2289h xc2000 family / high line functional description data sheet 83 v1.3, 2011-07 3.19 parallel ports the xc228xh provides up to 119 i/o lines which are organized into 11 input/output ports and 2 input ports. all port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port cont rol registers. this co nfiguration selects the direction (input/output), push/pull or open-drain operation, activation of pull devices, and edge characteristics (shape) and driver char acteristics (output current) of the port drivers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. during the in ternal reset, all port pins are configured as inputs without pull devices active. all port lines have alternate input or out put functions associat ed with them. these alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. for this reason, certain functions appear several times in table 10 . all port lines that are not used for alternate functions may be used as general purpose i/o lines. table 10 summary of the xc228xh?s ports port width i/o connected modules p0 8 i/o ebc (a7...a0), ccu6, usic, can p1 8 i/o ebc (a15...a8), ccu6, usic p2 14 i/o ebc (ready, bhe , a23...a16, ad15.. .ad13, d15...d13), can, cc2, gpt12e, usic, dap/jtag p3 8 i/o can, usic p4 8 i/o ebc (cs 4 ...cs0 ), cc2, can, gpt12e, usic p5 16 i analog inputs, ccu6, dap/jtag, gpt12e, can, cc1 p6 4 i/o adc, can, gpt12e p7 5 i/o can, gpt12e, scu, dap/jtag, ccu6, adc, usic p8 i/o ccu6, dap/jtag, cc1, usic p9 8 i/o ccu6, dap/jtag, can, eray, cc1 p10 16 i/o ebc (ale, rd , wr , ad12...ad0, d12...d0), ccu6, usic, dap/jtag, can, eray p11 6 i/o ccu6, usic, can p15 8 i analog inputs, gpt12e xc2288h, xc2289h xc2000 family / high line functional description data sheet 84 v1.3, 2011-07 3.20 power management the xc228xh provides the means to control the power it consumes either at a given time or averaged over a certain duration. three mechanisms can be used (and partly in parallel): ? supply voltage management permits the temporary reduction of the supply voltage of major parts of the logic or even its comp lete disconnection. this drastically reduces the power consumed because it eliminat es leakage current, particularly at high temperature. several power reduction modes provide th e best balance of power reduction and wake-up time. ? clock generation management controls the frequency of internal and external clock signals. clock signals for currently inactive parts of logic are disabled automatically. the user can drastically reduce the consumed power by reducing the xc228xh system clock frequency. external circuits can be controlled using the programmable frequency output extclk. ? peripheral management permits temporary disabling of peripheral modules. each peripheral can be disabled and enabled separ ately. the cpu can be switched off while the peripherals can continue to operate. wake-up from power reduction modes can be triggered either externally with signals generated by the external system, or inter nally by the on-chip wake-up timer. this supports intermittent operation of the xc 228xh by generating cyclic wake-up signals. full performance is available to quickly react to action requests while the intermittent sleep phases greatly reduce the av erage system power consumption. note: when selecting the supply voltage and the clock source and generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states. recommended sequences are provided which ensure the intended operation of power supply system and clock system. please refer to th e programmer?s guide. xc2288h, xc2289h xc2000 family / high line functional description data sheet 85 v1.3, 2011-07 3.21 instruction set summary table 11 lists the instructi ons of the xc228xh. the addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the ?instruction set manual? . this document also provides a detailed description of each instruction. table 11 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16- xc2288h, xc2289h xc2000 family / high line functional description data sheet 86 v1.3, 2011-07 rol/ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) sh ift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs/z move byte operand to word op. with sign/zero extension 2 / 4 jmpa/i/r jump absolute/indirect/re lative if condition is met 4 jmps jump absolute to a code segment 4 jb(c) jump relative if direct bit is set (and clear bit) 4 jnb(s) jump relative if direct bit is not set (and set bit) 4 calla/i/r call absolute/indirect/relativ e subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push/pop push/pop direct word r egister onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret(p) return from intra-segment subroutine (and pop direct word regi ster from system stack) 2 rets return from inter-segment subroutine 2 reti return from interrupt service subroutine 2 sbrk software break 2 srst software reset 4 idle enter idle mode 4 pwrdn unused instruction 1) 4 srvwdt service watchdog timer 4 diswdt/enwdt disable/enable watchdog timer 4 einit end-of-initialization register lock 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 table 11 instruction set summary (cont?d) mnemonic description bytes xc2288h, xc2289h xc2000 family / high line functional description data sheet 87 v1.3, 2011-07 nop null operation 2 comul/comac multiply (and accumulate) 4 coadd/cosub add/subtract 4 co(a)shr (arithmetic) shift right 4 coshl shift left 4 coload/store load accumulator/store mac register 4 cocmp compare 4 comax/min maximum/minimum 4 coabs/cornd absolute value/round accumulator 4 comov data move 4 coneg/nop negate accumulator/null operation 4 1) the enter power down mode instruction is not used in the xc228xh, due to the enhanced power control scheme. pwrdn will be correctly dec oded, but will trigger no action. table 11 instruction set summary (cont?d) mnemonic description bytes xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 88 v1.3, 2011-07 4 electrical parameters the operating range for the xc228xh is defined by its electrical parameters. for proper operation the specified limits must be respected when integrating the device in its target environment. 4.1 general parameters these parameters are valid for all subseq uent descriptions, un less otherwise noted. note: stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other c onditions above those indicated in the operational sections of this specificatio n is not implied. exposure to absolute maximum rating conditions for an exte nded time may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 12 absolute maximum rating parameters parameter symbol values unit note / test condition min. typ. max. output current on a pin when high value is driven i oh sr -30 ?? ?? i ov sr -10 ? v in is out of the absolute maximum rating range. in this case the current must be limited to the listed values by design measures. absolute sum of overload currents i ov | sr ?? t j sr -40 ? t st sr -65 ? v ddp sr -0.5 ? v in sr -0.5 ? v ddp + 0.5 v v in v ddp(max) xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 89 v1.3, 2011-07 4.1.1 operating conditions the following operating conditions must not be exceeded to ensure correct operation of the xc228xh. all parameters spec ified in the following secti ons refer to these operating conditions, unless otherwise noticed. note: typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum para meter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. additional details are described where applicable. table 13 operating conditions parameter symbol values unit note / test condition min. typ. max. voltage regulator buffer capacitance for dmp_m c evrm sr 1.0 ? c evr1 sr 0.68 ? c l sr ? ? f sys sr ?? i ova sr -2 ? i ovd sr -5 ? k ova cc ? i ov < 0 ma; not subject to production test ? i ov > 0 ma; not subject to production test xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 90 v1.3, 2011-07 overload current coupling factor for digital i/o pins k ovd cc ? i ov < 0 ma; not subject to production test ? i ov > 0 ma; not subject to production test absolute sum of overload currents i ov | sr ?? v ddim cc ? ? v ddi1 cc ? ? v ddp sr 3.0 ? v ss sr ? ? v ddim and v ddi1 pin to keep the resistance of the board tracks below 2 ohm. connect all v ddi1 pins together. the minimum capacitance value is required for proper operation under all conditions (e.g. temperature). higher values slightly increase the startup time. 2) use one capacitor for each pin. 3) this is the reference load. for big ger capacitive loads, use the derating factors listed in the pad properties section. 4) the timing is valid for pin drivers operating in default current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ). 5) the operating frequency range may be reduced for specific device types. this is indicated in the device designation (...fxxl). 80 mhz devices are marked ...f80l. 6) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ihmax ( i ov > 0) or v ov < v ilmin (( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma. the supply voltages must remain within the specified limits. proper operation under overload conditions depen ds on the application. overload conditions must not occur on pin xtal1 (powered by v ddim ). table 13 operating conditions (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 91 v1.3, 2011-07 7) an overload current ( i ov ) through a pin injects a certain error current ( i inj ) into the adjacent pins. this error current adds to the respective pins leakage current ( i oz ). the amount of error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is inverse compared to the polarity of the overload current that produces it.the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error current may distort the input voltage on analog inputs. 8) value is controlled by on-chip regulator xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 92 v1.3, 2011-07 4.2 voltage range definitions the xc228xh timing depends on the supply voltage. if such a dependency exists the timing values are given for 2 voltage ar eas commonly used. t he voltage areas are defined in the following tables. 4.2.1 parameter interpretation the parameters listed in the following includ e both the characteristics of the xc228xh and its demands on the system. to aid in correctly in terpreting the pa rameters when evaluating them for a design, they are ma rked accordingly in the column ?symbol?: cc ( c ontroller c haracteristics): the logic of the xc228xh provides sig nals with the specified characteristics. sr ( system r equirement): the external system must pr ovide signals with the specif ied characteristics to the xc228xh. table 14 upper voltage range definition parameter symbol values unit note / test condition min. typ. max. digital supply voltage for io pads and voltage regulators v ddp sr 4.5 5 5.5 v table 15 lower voltage range definition parameter symbol values unit note / test condition min. typ. max. digital supply voltage for io pads and voltage regulators v ddp sr 3.0 3.3 4.5 v xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 93 v1.3, 2011-07 4.3 dc parameters these parameters are static or average valu es that may be exceeded during switching transitions (e.g. output current). the xc228xh can operate within a wide supply voltage range from 3.0 v to 5.5 v. however, during operation this supply volt age must remain within 10 percent of the selected nominal supply voltage. it cannot vary across the full operating voltage range. because of the supply voltage restrictio n and because electrical behavior depends on the supply voltage, the paramet ers are specified separately for the upper and the lower voltage range. during operation, the supply voltages may only change with a maximum speed of dv/dt < 1 v/ms. leakage current is strongly dependent on t he operating temperature and the voltage level at the respective pin. the maximum values in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. the value for the leakage current in an a pplication can be determined by using the respective leakage derating formula (see tables) with values from that application. the pads of the xc228xh are designed to operate in various driver modes. the dc parameter specifications refer to the pad current limits specified in section 4.7.4 . xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 94 v1.3, 2011-07 pullup/pulldown device behavior most pins of the xc228xh feature pullup or pulldown devices. for some special pins these are fixed; for the port pins t hey can be selected by the application. the specified current values indicate how to load the respective pin depending on the intended signal level. figure 14 shows the current paths. the shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values. figure 14 pullup/pulldown current definition mc_xc2x_pull v ddp v ss pullup pulldown xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 95 v1.3, 2011-07 4.3.1 dc parameters for upper voltage area keeping signal levels within the limits spec ified in this table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . note: operating conditions apply. table 16 is valid under the following conditions: v ddp typ. 5 v; v ddp v ddp table 16 dc characteristics for upper voltage range parameter symbol values unit note / test condition min. typ. max. pin capacitance (digital inputs/outputs). to be doubled for double bond pins. 1) c io cc ?? v ddp ?? r s =0ohm absolute input leakage current on pins of analog ports 3) | i oz1 | cc ? v in > v ss v; v in < v ddp absolute input leakage current for all other pins. to be doubled for double bond pins. 3)1)4) | i oz2 | cc ? t j v in > v ss v; v in < v ddp ? t j v in > v ss v; v in < v ddp pull level force current 5) | i plf | sr 250 ?? v in v ihmin (pulldown _enabled) ; v in v ilmax (pull up_enabled) pull level keep current 6) | i plk | sr ?? v in v ihmin (pull up_enabled) ; v in v ilmax (pull down_enabled) input high voltage (all except xtal1) v ih sr 0.7 x v ddp ? v ddp + 0.3 v input low voltage (all except xtal1) v il sr -0.3 ? v ddp v xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 96 v1.3, 2011-07 output high voltage 7) v oh cc v ddp - 1.0 ?? i ohmax v ddp - 0.4 ?? i ohnom 8) output low voltage 7) v ol cc ?? i olnom 9) ?? i olmax 1) because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. for a list of affected pins refer to the pin definitions table in chapter 2. 2) not subject to production test - ve rified by design/characterization. h ysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 3) if the input voltage exceeds the respecti ve supply voltage due to ground bouncing ( v in < v ss ) or supply ripple ( v in > v ddp ), a certain amount of current may flow through the protection diodes. this current adds to the leakage current. an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 4) the given values are worst-case val ues. in production test, this leakage current is only tested at 125 c; other values are ensured by correlation. for derating, plea se refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 x e (1.5 + 0.028 x tj>) [ v ddp - v pin [v]): i oz = i oztempmax - (1.6 x dv) ( v ol -> v ss , v oh -> v ddp ). however, only the levels for nominal output currents are verified. table 16 dc characteristics for upper voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 97 v1.3, 2011-07 4.3.2 dc parameters for lower voltage area keeping signal levels within the limits spec ified in this table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . note: operating conditions apply. table 17 is valid under the following conditions: v ddp typ. 3.3 v; v ddp v ddp table 17 dc characteristics for lower voltage range parameter symbol values unit note / test condition min. typ. max. pin capacitance (digital inputs/outputs). to be doubled for double bond pins. 1) c io cc ?? v ddp ?? r s =0ohm absolute input leakage current on pins of analog ports 3) | i oz1 | cc ? v in > v ss v; v in < v ddp absolute input leakage current for all other pins. to be doubled for double bond pins. 3)1)4) | i oz2 | cc ? t j v in > v ss v; v in < v ddp ? t j v in > v ss v; v in < v ddp pull level force current 5) | i plf | sr 150 ?? v in v ihmin (pull down_enabled) ; v in v ilmax (pull up_enabled) pull level keep current 6) | i plk | sr ?? v in v ihmin (pull up_enabled) ; v in v ilmax (pull down_enabled) input high voltage (all except xtal1) v ih sr 0.7 x v ddp ? v ddp + 0.3 v xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 98 v1.3, 2011-07 input low voltage (all except xtal1) v il sr -0.3 ? v ddp v output high voltage 7) v oh cc v ddp - 1.0 ?? i ohmax v ddp - 0.4 ?? i ohnom 8) output low voltage 7) v ol cc ?? i olnom 9) ?? i olmax 1) because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. for a list of affected pins refer to the pin definitions table in chapter 2. 2) not subject to production test - ve rified by design/characterization. h ysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 3) if the input voltage exceeds the respecti ve supply voltage due to ground bouncing ( v in < v ss ) or supply ripple ( v in > v ddp ), a certain amount of current may flow through the protection diodes. this current adds to the leakage current. an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 4) the given values are worst-case val ues. in production test, this leakage current is only tested at 125 c; other values are ensured by correlation. for derating, plea se refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 x e (1.5 + 0.028 x tj>) [ v ddp - v pin [v]): i oz = i oztempmax - (1.6 x dv) ( v ol -> v ss , v oh -> v ddp ). however, only the levels for nominal output currents are verified. table 17 dc characteristics for lower voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 99 v1.3, 2011-07 4.3.3 power consumption the power consumed by the xc228xh depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. the power consumption specified here c onsists of two components: ? the switching current i s depends on the device activity ? the leakage current i lk depends on the device temperature to determine the actual power consumption, always both components, switching current i s and leakage current i lk must be added: i ddp = i s + i lk . note: the power consumption values are not subject to production test. they are verified by design/characterization. to determine the total power consumpti on for dimensioning the external power supply, also the pad driver currents must be considered. the given power consumption parameters and their values refer to specific operating conditions: ? active mode : regular operation, i.e. peripherals are active, code execution out of flash. ? stopover mode : crystal oscillator and pll stopped, flash switched off, clock in domain dmp_1 stopped. ? standby mode : voltage domain dmp_1 switched off complete ly, power supply control switched off. dmp_m domain is supplied by ultra lo w power electronic voltage regulator (ulpevr). the alternate regul ator evr_m is switched off. note: the maximum values cover the comp lete specified operating range of all manufactured devices. the typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperat ure, application-oriented activity. after a power reset, the decoupling capacitors for v ddim and v ddi1 are charged with the maximum possible current. for additional information, please refer to section 5.2 , thermal considerations . note: operating conditions apply. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 100 v1.3, 2011-07 active mode power supply current the actual power supply current in active mode not only depends on the system frequency but also on the configuration of the xc228xh?s subsystem. besides the power consumed by the device logic the power supply pins also provide the current that flows through the pin output drivers. a small current is consumed because the drivers? input stages are switched. the io power domains can be supplied separately. power domain a ( v ddpa ) supplies the a/d converters and port 6. power domain b ( v ddpb ) supplies the on-chip evvrs and all other ports. table 18 switching power consumption parameter symbol values unit note / test condition min. typ. max. power supply current (active) with all peripherals active and evvrs on 1) 1) if the flexray module clock (running @ 80 mhz) is turned off (kscfg.moden=0) the value is reduced by 15 ma. i sact_fr cc ? f sys 2) 2) f sys in mhz 40 + 1.4 x f sys 2) ma power_mode= active ; voltage_range= both 3)4)5) 3) the pad supply voltage pins ( v ddpb ) provide the input current for the on-chip evvrs and the current consumed by the pin output drivers. a small current is consumed because t he drivers input stages are switched. in fast startup mode (with the flash modules deactivated), the typical current is reduced to 3 + 0.6 x f sys . 4) please consider the additional conditions described in section "active mode power supply current". 5) the pad supply voltage has only a minor influence on this parameter. power supply current in standby mode i ssb cc ? v ddpb (swd) and v ddim (pvc_m) are off. leaving swd and pvc_m active adds another 90 ? i sso cc ? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 101 v1.3, 2011-07 during operation domain a draws a maximu m current of 1.5 ma for each active a/d converter module from v ddpa . in fast startup mode (with the flash modules deactivated), the typi cal current is reduced to 3 + 0.6 f sys ma. figure 15 supply current in active mode as a function of frequency note: operating conditions apply. mc_xc2xh_is_fr f sys [mhz] i s [ma] 20 40 80 20 40 80 60 100 120 140 180 i sact_frtyp i sact_frmax 60 160 100 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 102 v1.3, 2011-07 note: a fraction of the leakage current flows through domain dmp_a (pin v ddpa ). this current can be calculated as 7,000 e - , with = 5000 / (273 + 1.3 t j ). for t j = 150c, this results in a current of 160 a. the leakage power consumption can be calculated according to the following formulas: i lk0 = 500,000 t j ) parameter b must be replaced by ? 1.0 for typical values ? 1.6 for maximum values i lk1 = 600,000 t j ) parameter b must be replaced by ? 1.1 for typical values ? 1.4 for maximum values table 19 leakage power consumption parameter symbol values unit note / test condition min. typ. max. leakage supply current (dmp_1 off) 1)2) i lk0 cc ? t j =25c ? t j =85c ? t j =125c ? t j =150c leakage supply current (dmp_1 powered) 1)2) 1) the supply current caused by leak age depends mainly on the junction temperature and the supply voltage. the temperature difference between the junction temperature t j and the ambient temperature t a must be taken into account. as this fraction of the supply current does not depend on device activity, it must be added to other power consumption values. 2) all inputs (including pins configured as inputs) are set at 0 v to 0.1 v or at v ddp - 0.1 v to v ddp and all outputs (including pins configured as outputs) are disconnected. i lk1 cc ? t j =25c ? t j =85c ? t j =125c ? t j =150c xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 103 v1.3, 2011-07 figure 16 leakage supply current as a function of temperature mc_xc2xh_ilk150 t j [c] i lk [ma] 2 6 10 050 150 100 -50 4 8 12 i lk0max i lk0typ i lk1max i lk1typ 14 18 16 20 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 104 v1.3, 2011-07 4.4 analog/digital converter parameters these parameters describe the conditions for optimum adc performance. note: operating conditions apply. table 20 adc parameters parameter symbol values unit note / test condition min. typ. max. switched capacitance at an analog input c ainsw cc ?? c aint cc ?? c arefsw cc ?? c areft cc ?? ea dnl | cc ? ea gain | cc ? ea inl | cc ? ea off | cc ? f adci sr 0.5 ? ? r ain cc ?? r aref cc ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 105 v1.3, 2011-07 broken wire detection delay against vagnd 1) t bwg cc ?? t bwr cc ?? t c8 cc (11 + stc) x t adci + 2 x t sys ?? t c10 cc (13 + stc) x t adci + 2 x t sys ?? ? t waf cc ?? t was cc ?? v agnd sr v ss - 0.05 ? v ain sr v agnd ? v aref v 5) analog reference voltage v aref sr v agnd + 1.0 ? v ddpa + 0.05 v 1) this parameter includes the sample time (also the a dditional sample time specified by stc), the time to determine the digital result and the time to load the result register with the conversion result. values for the basic clock t adci depend on programming. 2) the broken wire detection delay against v agnd is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 v aref is measured in numbers of c onsecutive precharge cycles at a conversion rate of not more than 10 table 20 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 106 v1.3, 2011-07 figure 17 equivalent circuitry for analog inputs 4) tue is tested at v aref = v ddpa = 5.0 v, v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. the specified tue is valid only if the absolute sum of input overload currents on analog port pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the measurement time. 5) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. a/d converter mcs05570 r sour ce v ain c ext c aint c ains - r ain, on c ains xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 107 v1.3, 2011-07 sample time and conversion time of the xc228xh?s a/d converters are programmable. the timing above can be calculated using table 21 . the limit values for f adci must not be exceeded when selecting the prescaler value. converter timing example a: converter timing example b: table 21 a/d converter computation table globctr.5-0 (diva) a/d converter analog clock f adci inpcrx.7-0 (stc) sample time 1) t s 1) the selected sample time is doubled if broken wire detection is active (due to the presampling phase). 000000 b f sys 00 h t adci f sys / 2 01 h t adci f sys / 3 02 h t adci f sys / (diva+1) : t adci f sys / 63 fe h t adci f sys / 64 ff h t adci f sys = 100 mhz (i.e. t sys = 10 ns), diva = 03 h , stc = 00 h analog clock f adci = f sys / 4 = 25 mhz, i.e. t adci = 40 ns sample time t s = t adci conversion 10-bit: t c10 = 13 t adci + 2 t sys = 13 conversion 8-bit: t c8 = 11 t adci + 2 t sys = 11 f sys = 40 mhz (i.e. t sys = 25 ns), diva = 02 h , stc = 03 h analog clock f adci = f sys / 3 = 13.3 mhz, i.e. t adci = 75 ns sample time t s = t adci conversion 10-bit: t c10 = 16 t adci + 2 t sys = 16 conversion 8-bit: t c8 = 14 t adci + 2 t sys = 14 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 108 v1.3, 2011-07 4.5 system parameters the following parameters specify several aspe cts which are important when integrating the xc228xh into an application system. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 22 various system parameters parameter symbol values unit note / test condition min. typ. max. short-term deviation of internal clock source frequency 1) 1) the short-term frequency deviation refe rs to a timeframe of a few hours and is measured relative to the current frequency at the beginning of the respective timeframe. this parameter is useful to determine a time span for re-triggering a lin synchronization. f int cc -1 ? t j f int cc 4.8 5.0 5.2 mhz wakeup clock source frequency 2) f wu cc 400 ? ? ? ? t spo cc 1.9 2.6 3.2 ms f wu = 500 khz startup time from standby mode with code execution from flash t ssb cc 3.2 4.2 4.9 ms f wu = 140 khz 2.0 2.7 3.3 ms f wu = 500 khz startup time from stopover mode with code execution from psram t sso cc 11 / f wu 3) ? f wu 3) v pvc cc v lv - 0.03 v lv v lv + 0.07 4) v 5) supply watchdog (swd) supervision level v swd cc v lv - 0.10 6) v lv v lv + 0.15 v voltage_range= lower 5) v lv - 0.15 v lv v lv + 0.15 v voltage_range= upper 5) xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 109 v1.3, 2011-07 conditions for t spo timing measurement the time required for the transition from power-on to base mode is called t spo . it is measured under the following conditions: precondition: the pad supply is valid, i.e. v ddpb is above 3.0v and remains above 3.0v even though the xc228xh is starti ng up. no debugger is attached. start condition: power-on reset is removed (porst = 1). end condition: external pin toggle caused by first user instruction executed from flash after startup. conditions for t ssb timing measurement the time required for the transition from standby to base mode is called t ssb . it is measured under the following conditions: precondition: the standby mode has been entered using the procedure defined in the programmer?s guide. start condition: pin toggle on esr pin triggering the startup sequence. end condition: external pin toggle caused by first user instruction executed from flash after startup. conditions for t sso timing measurement the time required for the transition from stopover to stopover waked-up mode is called t sso . it is measured under the following conditions: precondition: the stopover mode has been entered using the procedure defined in the programmer?s guide. start condition: pin toggle on esr pin triggering the startup sequence. end condition: external pin toggle caused by first user instruction executed from psram after startup. 2) this parameter is tested for the fastest and the slowes t selection. the medium selections are not subject to production test - verified by design/characterization 3) f wu in mhz 4) this value includes a hysteresis of approximately 50 mv for rising voltage. 5) v lv = selected swd voltage level 6) the limit v lv - 0.10 v is valid for the ok1 leve l. the limit for the ok2 level is v lv - 0.15 v. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 110 v1.3, 2011-07 coding of bit fields levxv in swd and pvc configuration registers table 23 coding of bit fields levxv in register swdcon0 code default voltage level notes 1) 1) the indicated default levels are selected automatically after a power reset. 0000 b 2.9 v 0001 b 3.0 v lev1v: reset request 0010 b 3.1 v 0011 b 3.2 v 0100 b 3.3 v 0101 b 3.4 v 0110 b 3.6 v 0111 b 4.0 v 1000 b 4.2 v 1001 b 4.5 v lev2v: no request 1010 b 4.6 v 1011 b 4.7 v 1100 b 4.8 v 1101 b 4.9 v 1110 b 5.0 v 1111 b 5.5 v table 24 coding of bit fields levxv in registers pvcyconz code default voltage level notes 1) 1) the indicated default levels are selected automatically after a power reset. 000 b 0.95 v 001 b 1.05 v 010 b 1.15 v 011 b 1.25 v 100 b 1.35 v lev1v: reset request 101 b 1.45 v lev2v: interrupt request 2) 110 b 1.55 v 111 b 1.65 v xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 111 v1.3, 2011-07 2) due to variations of the tolerance of both the embedded voltage regulators (evr) and the pvc levels, this interrupt can be triggered inadvertently, even though the core voltage is within the normal range. it is, therefore, recommended not to use this warning level. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 112 v1.3, 2011-07 4.6 flash memory parameters the xc228xh is delivered with all flash sector s erased and with no protection installed. the data retention time of the xc228xh?s fl ash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the flash memory has been erased and programmed. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 25 flash parameters parameter symbol values unit note / test condition min. typ. max. parallel flash module program/erase limit depending on flash read activity n pp sr ?? n fl_rd ?? n fl_rd >1 flash erase endurance for security pages n sec sr 10 ?? t ret n wsflas h sr 1 ?? f sys ?? f sys ?? f sys ?? f sys >17mhz flash wait state extension 4) n wsfle sr 0 ?? f sys ?? f sys >80mhz erase time per sector/page t er cc ? t pr cc ? t ret cc 20 ?? n er n dd sr 32 ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 113 v1.3, 2011-07 access to the xc228xh flash modules is controlled by the im b. built-in prefetch mechanisms optimize the performance for sequential access. flash access waitstates only affect non-sequential access. due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates. number of erase cycles n er sr ?? t ret ?? t ret table 25 flash parameters (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 114 v1.3, 2011-07 4.7 ac parameters these parameters describe the dynamic behavior of the xc228xh. 4.7.1 testing waveforms these values are used for characterization and production testing (except pin xtal1). figure 18 input output waveforms figure 19 floating waveforms mcd05556c 0.3 v ddp input signal (driven by tester) output signal (measured) hold time output delay output delay hold time output timings refer to the rising edge of clkout. input timings are calculated from the time, when the input signal reaches v ih or v il , respectively. 0.2 v ddp 0.8 v ddp 0.7 v ddp mca05565 timing reference points v load + 0.1 v v load - 0.1 v v oh - 0.1 v v ol + 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 20 ma). xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 115 v1.3, 2011-07 4.7.2 definition of internal timing the internal operation of the xc228xh is controlled by the internal system clock f sys . because the system clock signal f sys can be generated from a number of internal and external sources using different mechanism s, the duration of the system clock periods (tcss) and their variation (as well as th e derived external timing) depend on the mechanism used to generate f sys . this must be considered when calculating the timing for the xc228xh. figure 20 generation mechanisms for the system clock note: the example of pll operation shown in figure 20 uses a pll factor of 1:4; the example of prescaler operation us es a divider factor of 2:1. the specification of the external timing (a c characteristics) depends on the period of the system clock (tcs). m c _ xc 2 x_ cl oc kgen phase locked loop operation (1:n) f in direct clock drive (1:1) prescaler operation (n:1) f sys f in f sys f in f sys tcs tcs tcs xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 116 v1.3, 2011-07 direct drive when direct drive op eration is selected (syscon0.clksel = 11 b ), the system clock is derived directly from the input clock signal clkin1: f sys = f in . the frequency of f sys is the same as the frequency of f in . in this case the high and low times of f sys are determined by the duty cycle of the input clock f in . selecting bypass operation from the xtal1 1) input and using a divider factor of 1 results in a similar configuration. prescaler operation when prescaler operation is selected (syscon0.clksel = 10 b , pllcon0.vcoby = 1 b ), the system clock is derived either from the crystal oscillat or (input clock signal xtal1) or from the internal clock source through the output prescaler k1 (= k1div+1): f sys = f osc / k1. if a divider factor of 1 is selected, the frequency of f sys equals the frequency of f osc . in this case the high and low times of f sys are determined by the duty cycle of the input clock f osc (external or internal). the lowest system clock fr equency results from selecting the maximum value for the divider factor k1: f sys = f osc / 1024. 4.7.2.1 phase locked loop (pll) when pll operation is sele cted (syscon0.clksel = 10 b , pllcon0.vcoby = 0 b ), the on-chip phase locked loop is enabled and provides the system clock. the pll multiplies the input frequency by the factor f ( f sys = f in f ). f is calculated from the input divider p (= pdiv+1), the multiplication factor n (= ndiv+1), and the output divider k2 (= k2div+1): (f = n / (p f sys so that it is locked to f in . the slight variation causes a jitter of f sys which in turn affects the duration of individual tcss. 1) voltages on xtal1 must comply to the core supply voltage v ddim . xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 117 v1.3, 2011-07 the timing in the ac characteristics refers to tcss. timing must be calculated using the minimum tcs possible under the given circumstances. the actual minimum value for tcs depends on the jitter of the pll. because the pll is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitte r is limited. this means that the relative deviation for periods of more than one tcs is lower than for a single tcs (see formulas and figure 21 ). this is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. for all slower operations and lo nger periods (e.g. pulse train generation or measurement, lower baudrates, et c.) the deviation caused by the pll jitter is negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the respective timeframe. the vco outp ut clock is divided by the output prescaler k2 to generate the system clock signal f sys . the number of vco cycles is k2 t , where t is the number of consecutive f sys cycles (tcs). the maximum accumulated ji tter (long-term jitter) d tmax is defined by: d tmax [ns] = f sys ) + 4.3) this maximum value is applicable, if ei ther the number of clock cycles t > ( f sys / 1.2) or the prescaler value k2 > 17. in all other cases for a timeframe of t d t [ns] = d tmax f sys - 1) + 0.058 f sys in [mhz] in all formulas. example, for a period of 3 tcss @ 33 mhz and k2 = 4: d max = xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 118 v1.3, 2011-07 figure 21 approximated accumulated pll jitter note: the specified pll jitter values are va lid if the capacitive load per pin does not exceed c l =20pf. the maximum peak-to-peak noise on th e pad supply voltage (measured between v ddpb pin 144 and v ss pin 1) is limited to a peak-to-peak voltage of v pp = 50 mv. this can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using pcb supply and ground planes. pll frequency band selection different frequency bands can be selected for the vco so that the operation of the pll can be adjusted to a wide range of input and output frequencies: mc_xc 2x_jitter cycles t 0 1 2 3 4 5 6 7 8 acc. jitter d t 20 40 60 80 100 ns f sys = 66 mhz 1 f vco = 132 mhz f vco = 66 mhz 9 f sys = 33 mhz xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 119 v1.3, 2011-07 flexray pll parameters this pll unit is dedicated for usage with the flexray module. flexray operation requires a high precision clock signal to fulf il the protocol timing requirements. if the system clock is generated by use of a qua rtz it is mandatory to adjust the quartz parameters in your target system. please refer also to chapter 4.7.3 for details. 4.7.2.2 wakeup clock when wakeup operation is selected (syscon0.clksel = 00 b ), the system clock is derived from the low-frequency wakeup clock source: f sys = f wu . in this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption. table 26 system pll parameters parameter symbol values unit note / test condition min. typ. max. vco output frequency f vco cc 50 ? vcosel = 00b; vcomode = controlled 10 ? vcosel = 00b; vcomode = free running 100 ? vcosel = 01b; vcomode = controlled 20 ? vcosel = 01b; vcomode = free running table 27 flexray pll parameters parameter symbol values unit note / test condition min. typ. max. vco output frequency f vca cc 480 ? vcomode =con trolled 80 ? vcomode =fre e running xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 120 v1.3, 2011-07 4.7.2.3 selecting and changing the operating frequency when selecting a clock source and the clock generation method, the required parameters must be carefully written to t he respective bit fields, to avoid unintended intermediate states. many applications change the fr equency of the system clock ( f sys ) during operation in order to optimize system performance and power consumption. ch anging the operating frequency also changes the switching currents, which influences the power supply. to ensure proper operation of the on-chip evrs while they generate the core voltage, the operating frequency shall only be changed in certain steps. this prevents overshoots and undershoots of the supply voltage. to avoid the indicated problems, recommen ded sequences are provided which ensure the intended operation of the clock syst em interacting with the power system. please refer to the programmer?s guide. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 121 v1.3, 2011-07 4.7.3 external clock input parameters these parameters specify the external clock generation for the xc228xh. the clock can be generated in two ways: ? by connecting a crystal or ceramic resonator to pins xtal1/xtal2 ? by supplying an external clock signal ? this clock signal can be supplied either to pin xtal1 (core voltage domain) or to pin clkin1 or clkin2 (io voltage domain) if connected to clkin1 or clkin2, the i nput signal must reach the defined input levels v il and v ih . if connected to xtal1, a minimum amplitude v ax1 (peak-to-peak voltage) is sufficient for the operatio n of the on-chip oscillator. note: the given clock timing parameters ( t 1 t 4 ) are only valid for an external clock input signal. note: operating conditions apply. table 28 external clock input characteristics parameter symbol values unit note / test condition min. typ. max. oscillator frequency f osc sr 4 ? ? i il | cc ?? t 1 sr 6 ?? t 2 sr 6 ?? t 3 sr ? t 4 sr ? v ax1 sr 0.3 x v ddim ?? f osc f osc <16mhz 0.4 x v ddim ?? f osc f osc <25mhz 0.5 x v ddim ?? f osc f osc v ix1 sr -1.7 + v ddim ? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 122 v1.3, 2011-07 note: for crystal or ceramic resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimu m parameters for o scillator operation. the manufacturers of cryst als and ceramic resonato rs offer an oscillator evaluation service. this evaluation checks the crysta l/resonator specification limits to ensure a reliable oscillator operation. figure 22 external clock drive xtal1 1) the amplitude voltage v ax1 refers to the offset voltage v off . this offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by v ix1 . 2) overload conditions must not occur on pin xtal1. mc_ extclock t 1 t 2 t osc = 1/ f osc t 3 t 4 v off v ax1 0.1 v ax1 0.9 v ax1 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 123 v1.3, 2011-07 4.7.4 pad properties the output pad drivers of t he xc228xh can operate in several user-selectable modes. strong driver mode allows controlling ex ternal components requiring higher currents such as power bridges or leds. reducing the driving power of an output pad reduces electromagnetic emissions (e me). in strong driver mode, selecting a slower edge reduces eme. the dynamic behavior, i.e. the rise time and fall time, depends on the applied external capacitance that must be charged and discharged. timing values are given for a capacitance of 20 pf, unless otherwise noted. in general, the performance of a pad driver depends on the available supply voltage v ddp . therefore the following tables list the p ad parameters for the upper voltage range and the lower voltage range, respectively. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 29 is valid under the following conditions: v ddp typ. 5 v; v ddp v ddp table 29 standard pad paramete rs for upper voltage range parameter symbol values unit note / test condition min. typ. max. maximum output driver current (absolute value) 1) i omax cc ?? ?? ?? i onom cc ?? ?? ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 124 v1.3, 2011-07 rise and fall times (10% - 90%) t rf cc ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring output pins, the total output current in each direction ( i ol and -i oh ) must remain below 50 ma. table 29 standard pad paramete rs for upper voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 125 v1.3, 2011-07 table 30 standard pad paramete rs for lower voltage range parameter symbol values unit note / test condition min. typ. max. maximum output driver current (absolute value) 1) i omax cc ?? ?? ?? i onom cc ?? ?? ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 126 v1.3, 2011-07 rise and fall times (10% - 90%) t rf cc ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l ?? c l ns c l c l i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring output pins, the total output current in each direction ( i ol and -i oh ) must remain below 50 ma. table 30 standard pad paramete rs for lower voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 127 v1.3, 2011-07 4.7.5 external bus timing the following parameters specify the behavior of the xc228xh bus interface. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. figure 23 clkout signal timing note: the term clkout refers to the reference clock output signal which is generated by selecting f sys as the source signal for the clock output signal extclk on pin p2.8 and by enabling the high-speed clock driver on this pin. table 31 parameters parameter symbol values unit note / test condition min. typ. max. clkout cycle time 1) 1) the clkout cycle time is influenced by pll jitter. for longer periods the relative deviation decreases (see pll deviation formula). t 5 cc ? f sys ? t 6 cc 2 ?? t 7 cc 2 ?? t 8 cc ?? t 9 cc ?? t 5 t 6 t 7 t 8 t 9 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 128 v1.3, 2011-07 variable memory cycles external bus cycles of the xc 228xh are executed in five consecutive cycle phases (ab, c, d, e, f). the duration of each cycle phase is programmable (via the tconcsx registers) to adapt t he external bus cycles to the res pective external module (memory, peripheral, etc.). the duration of the access phase can optiona lly be controlled by the external module using the ready handshake input. this table provides a summary of the phases and the ranges for their length. note: the bandwidth of a parameter (from minimum to maximum value) covers the whole operating range (temper ature, voltage) as well as process variations. within a given device, however, this bandwidth is smaller than the specified range. this is also due to interdependencies between certain parameters. some of these interdependencies are described in add itional notes (see standard timing). note: operating conditions apply. table 33 is valid under the following conditions: c l = 20 pf; voltage_range= upper ; voltage_range= upper table 32 programmable bus cycle phases (see timing diagrams) bus cycle phase parameter valid values unit address setup phase, the standard duration of this phase (1 ? 2 tcs) can be extended by 0 ? 3 tcs if the address window is changed tpab 1 ? 2 (5) tcs command delay phase tpc 0 ? 3 tcs write data setup/mux tristate phase tpd 0 ? 1 tcs access phase tpe 1 ? 32 tcs address/write data hold phase tpf 0 ? 3 tcs table 33 external bus timing for upper voltage range parameter symbol values unit note / test condition min. typ. max. output valid delay for rd , wr (l /h ) t 10 cc ? t 11 cc ? t 12 cc ? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 129 v1.3, 2011-07 table 34 is valid under the following conditions: c l = 20 pf; voltage_range= lower ; voltage_range= lower address output valid delay for ad15 ... ad0 (mux mode) t 13 cc ? t 14 cc ? t 15 cc ? t 16 cc ? t 20 cc -2 6 8 ns output hold time for bhe , ale t 21 cc -2 6 10 ns address output hold time for ad15 ... ad0 t 23 cc -3 6 8 ns output hold time for cs t 24 cc -3 6 11 ns data output hold time for d15 ... d0 and ad15 ... ad0 t 25 cc -3 6 8 ns input setup time for ready, d15 ... d0, ad15 ... ad0 t 30 sr 25 15 ? t 31 sr 0 -7 ? table 33 external bus timing for upper voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 130 v1.3, 2011-07 table 34 external bus timing for lower voltage range parameter symbol values unit note / test condition min. typ. max. output valid delay for rd , wr (l /h ) t 10 cc ? t 11 cc ? t 12 cc ? t 13 cc ? t 14 cc ? t 15 cc ? t 16 cc ? t 20 cc -2 8 10 ns output hold time for bhe , ale t 21 cc -2 8 10 ns address output hold time for ad15 ... ad0 t 23 cc -3 8 10 ns output hold time for cs t 24 cc -3 8 11 ns data output hold time for d15 ... d0 and ad15 ... ad0 t 25 cc -3 8 10 ns input setup time for ready, d15 ... d0, ad15 ... ad0 t 30 sr 29 17 ? t 31 sr 0 -9 ? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 131 v1.3, 2011-07 figure 24 multiplexed bus cycle clkout tp ab tp c tp d tp e tp f ale t 21 t 11 a23-a16, bhe, csx t 11 / t 12 / t 14 rd wr(l/ h) t 20 t 10 data in ad15-ad0 (read) t 30 t 31 mc_x_ebcmux ad15-ad0 (write) t 13 t 15 t 25 t 13 t 23 data out low address high address low address t 24 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 132 v1.3, 2011-07 figure 25 demultiplexed bus cycle 4.7.5.1 bus cycle control with the ready input the duration of an external bus cycle can be controlled by the external circuit using the ready input signal. the polarity of this input signal can be selected. synchronous ready permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal clkout. an asynchronous ready signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the addi tional synchronization stage. the minimum address tp ab tp c tp d tp e tp f t 21 t 11 t 11 / t 12 / t 14 t 20 t 10 data in t 30 t 31 mc_x_ebcdemux t 16 t 25 clkout ale a23-a0, bhe, csx rd wr(l/ h) d15-d0 (read) d15-d0 (write) data out t 24 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 133 v1.3, 2011-07 duration of an asynchronous ready signal for safe synchronization is one clkout period plus the input setup time. an active ready signal can be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). if the next bus cycle is controlled by ready, an active ready signal must be disabled before the first valid sample point in the next bus cycle. this sample point depends on the programmed phases of the next cycle. figure 26 ready timing mc_ x_ebcready ready asynchron. not rdy ready data out t 25 t 30 d15-d0 (wri te) ready synchronous not rdy ready data in d15-d0 (read) t 10 rd, wr tp d tp e tp rdy tp f clkout t 20 t 30 t 31 t 31 t 30 t 31 t 30 t 31 t 30 t 31 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 134 v1.3, 2011-07 note: if the ready input is sampled inactive at the indicated sampling point (?not rdy?) a ready-controlled waitstate is inserted (tprdy), sampling the ready input active at the indicated sampling point (?ready?) terminates the curr ently running bus cycle. note the different sampling points for synchronous and asynchronous ready. this example uses one mandatory wait state (see tpe) before the ready input value is used. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 135 v1.3, 2011-07 4.7.6 synchronous serial interface timing the following parameters are applicable for a usic channel operated in ssc mode. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 35 is valid under the following conditions: c l =20pf; ssc =master; voltage_range= upper table 36 is valid under the following conditions: c l =20pf; ssc =master; voltage_range= lower table 35 usic ssc master mode timing for upper voltage range parameter symbol values unit note / test condition min. typ. max. slave select output selo active to first sclkout transmit edge t 1 cc t sys - 8 1) 1) t sys = 1 / f sys ?? t 2 cc t sys - 6 1) ?? t 3 cc -6 ? t 4 sr 31 ?? t 5 sr -4 ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 136 v1.3, 2011-07 table 37 is valid under the following conditions: c l =20pf; ssc = slave ; voltage_range= upper table 36 usic ssc master mode timing for lower voltage range parameter symbol values unit note / test condition min. typ. max. slave select output selo active to first sclkout transmit edge t 1 cc t sys - 10 1) 1) t sys = 1 / f sys ?? t 2 cc t sys - 9 1) ?? t 3 cc -7 ? t 4 sr 40 ?? t 5 sr -5 ?? table 37 usic ssc slave mode timi ng for upper voltage range parameter symbol values unit note / test condition min. typ. max. select input dx2 setup to first clock input dx1 transmit edge 1) t 10 sr 7 ?? t 11 sr 7 ?? t 12 sr 7 ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 137 v1.3, 2011-07 table 38 is valid under the following conditions: c l =20pf; ssc = slave ; voltage_range= lower data input dx0 hold time from clock input dx1 receive edge 1) t 13 sr 5 ?? t 14 cc 7 ? table 38 usic ssc slave mode timi ng for lower voltage range parameter symbol values unit note / test condition min. typ. max. select input dx2 setup to first clock input dx1 transmit edge 1) 1) these input timings are valid for asyn chronous input signal handling of slave select input, shift clock input, and receive data input (bits dxncr.dsen = 0). t 10 sr 7 ?? t 11 sr 7 ?? t 12 sr 7 ?? t 13 sr 5 ?? t 14 cc 8 ? table 37 usic ssc slave mode timi ng for upper voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 138 v1.3, 2011-07 figure 27 usic - ssc master/slave mode timing note: this timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. t 2 t 1 usic_ssc_tmgx.vsd clock output sclkout data output dout t 3 t 3 t 5 data valid t 4 fi rs t trans mi t edge data input dx0 select output selox active master mode timing slave mode timing t 11 t 10 clock input dx1 data output dout t 14 t 14 data valid data input dx0 select input dx2 active t 13 t 12 transmit edge: with this clock edge , transmit data is shifted to transmit data output . receive edge: with this clock edge, receive data at receive data input is latched . receive edge last receive edge inactive inactive transmit edge inactive inactive first transmit edge receive edge trans mi t edge last receive edge t 5 data valid t 4 data valid t 12 t 13 drawn for brgh .sclkcfg = 00 b . also valid for for sclkcfg = 01 b with inverted sclkout signal. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 139 v1.3, 2011-07 4.7.7 flexray interface timing the following parameters are applicable to the flexray channels. notes 1. these parameters are not subject to pro duction test but verified by design and/or characterization. 2. valid for flexray operation frequency 80 mhz. 3. valid for pad driver_strength=strong; driver_edge=sharp. 4. must use double pad (see chapter 2.1 ) when operated at 3.3 v. 5. operating conditions apply. table 39 eray flexray interface timing parameter symbol values unit note / test condition min. typ. max. time span from last bss to fes without the influence of quartz tolerance (d10bit_tx) 1) 1) pll jitter included. t 60 cc 997.75 ? f osc =20mhz; c l t f - t r | t 61_minus_ t62 cc ?? c l c l = 15pf, 20% x v ddp to 80% x v ddp , according to the flexray electrical physical layer specification v2.1 b. t 63 sr 966.5 ? f osc =20mhz rxd capture by fsample (rxda/rxdb => sampling flip-flop) (drxasym) 4) t 64_minus_ t65 cc ?? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 140 v1.3, 2011-07 figure 28 flexray timing txd t 60 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) e-ray_timing_16 rxd t 63 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) 0.9 v dd 0.1 v dd txd t 61 t 62 t sample 0.7 v dd 0.3 v dd rxd t 64 t 65 t sample xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 141 v1.3, 2011-07 4.7.8 debug interface timing the debugger can communicate with the xc228xh either via the 2-pin dap interface or via the standard jtag interface. debug via dap the following parameters are applicable for communication through the dap debug interface. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 40 is valid under the following conditions: c l = 20 pf; voltage_range= upper table 40 dap interface timing for upper voltage range parameter symbol values unit note / test condition min. typ. max. dap0 clock period 1) 1) see the dap chapter for clock rate restrictions in the active::idle protocol state. t 11 sr 25 ?? t 12 sr 8 ?? t 13 sr 8 ?? t 14 sr ?? t 15 sr ?? t 16 sr 3 ?? ?? t 17 sr 4 ?? ?? t 19 cc 19 21 ? ? xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 142 v1.3, 2011-07 table 41 is valid under the following conditions: c l = 20 pf; voltage_range= lower figure 29 test clock timing (dap0) table 41 dap interface timing for lower voltage range parameter symbol values unit note / test condition min. typ. max. dap0 clock period 1) 1) see the dap chapter for clock rate restrictions in the active::idle protocol state. t 11 sr 25 ?? t 12 sr 8 ?? t 13 sr 8 ?? t 14 sr ?? t 15 sr ?? t 16 sr 3 ?? ?? t 17 sr 4 ?? ?? t 19 cc 19 21 ? ? v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 143 v1.3, 2011-07 figure 30 dap timing host to device figure 31 dap timing device to host note: the transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram. debug via jtag the following parameters are applicable for communication through the jtag debug interface. the jtag module is fu lly compliant with ieee1149.1-2000. note: these parameters are not subject to pr oduction test but verified by design and/or characterization. note: operating conditions apply. table 42 is valid under the following conditions: c l = 20 pf; voltage_range= upper table 42 jtag interface timing for upper voltage range parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 50 ?? t 2 sr 16 ?? t 16 t 17 dap0 dap1 mc_ dap1_rx dap1 mc_dap1_tx t 11 t 19 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 144 v1.3, 2011-07 table 43 is valid under the following conditions: c l = 20 pf; voltage_range= lower tck low time t 3 sr 16 ?? t 4 sr ?? t 5 sr ?? t 6 sr 6 ?? t 7 sr 6 ?? t 8 cc ? t 9 cc ? t 10 cc ? t 18 cc 5 ?? table 43 jtag interface timing for lower voltage range parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 50 ?? t 2 sr 16 ?? t 3 sr 16 ?? t 4 sr ?? t 5 sr ?? t 6 sr 6 ?? table 42 jtag interface timing for upper voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 145 v1.3, 2011-07 figure 32 test clock timing (tck) tdi/tms hold after tck rising edge t 7 sr 6 ?? t 8 cc ? t 9 cc ? t 10 cc ? t 18 cc 5 ?? table 43 jtag interface timing for lower voltage range (cont?d) parameter symbol values unit note / test condition min. typ. max. mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 xc2288h, xc2289h xc2000 family / high line electrical parameters data sheet 146 v1.3, 2011-07 figure 33 jtag timing t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18 xc2288h, xc2289h xc2000 family / high line package and reliability data sheet 147 v1.3, 2011-07 5 package and reliability the xc2000 family devices use the pack age type pg-lqfp (plastic green - low profile quad flat package). the following sp ecifications must be regarded to ensure proper integration of the xc22 8xh in its target environment. 5.1 packaging these parameters specify the packaging rather than the silicon. note: to improve the emc behavior, it is recommended to connect the exposed pad to the board ground, independent of the thermal requirements. board layout examples are gi ven in an application note. package compatibility considerations the xc228xh is a member of the xc2000 fa mily of microcontrollers. it is also compatible to a certain extent with me mbers of similar families or subfamilies. each package is optimized for the device it houses. therefore, there may be slight differences between packages of the same pi n-count but for different device types. in particular, the size of the exposed pad (if present) may vary. table 44 package parameters (pg-lqfp-144-13) parameter symbol limit values unit notes min. max. exposed pad dimension ex p diss ? < 1 w? thermal resistance junction-ambient r xc2288h, xc2289h xc2000 family / high line package and reliability data sheet 148 v1.3, 2011-07 if different device types are considered or planned for an applicati on, it must be ensured that the board layout fits all packages under consideration. package outlines figure 34 pg-lqfp-144-13 (plastic green thin quad flat package) all dimensions in mm. you can find complete information about infineon packages, packing and marking in our infineon internet page ?packages?: http://www.infineon.com/packages 1) does not include plastic or metal protrusion of 0.25 max. per side bottom view 0.5 17.5 ?.05 0.22 144x cda-b m 0.08 c 0.08 1.6 max. 1.4 ?.05 0.1 0.05 d 20 1) a-b0.2 dh 4x 22 a-b0.2 d c 144x b a 20 1) 22 1 144 ex ey index marking index marking 1 exposed diepad 144 144x ?.15 0.6 h 0.15 -0.06 +0.05 pg-lqfp-144-4, -13-po v08 7? max. seating plane coplanarity stand off xc2288h, xc2289h xc2000 family / high line package and reliability data sheet 149 v1.3, 2011-07 5.2 thermal considerations when operating the xc228xh in a system, the to tal heat generated in the chip must be dissipated to the ambient environment to pr event overheating and the resulting thermal damage. the maximum heat that can be dissipated dep ends on the package and its integration into the target board. the ?thermal resistance r p int + p iostat + p iodyn ) r p int = v ddp i ddp (switching current and leakage current). the static external power consumption caus ed by the output drivers is defined as p iostat = v ddp - v oh ) i oh ) + v ol i ol ) the dynamic external power consumpt ion caused by the output drivers ( p iodyn ) depends on the capacitive load connected to the resp ective pins and their switching frequencies. if the total power di ssipation for a given system configur ation exceeds the defined limit, countermeasures must be taken to ensure proper system operation: ? reduce v ddp , if possible in the system ? reduce the system frequency ? reduce the number of output pins ? reduce the load on active output drivers xc2288h, xc2289h xc2000 family / high line package and reliability data sheet 150 v1.3, 2011-07 5.3 quality declarations the operation lifetime of the xc228xh depends on the applied temperature profile in the application. for a typical example, please refer to table 46 ; for other profiles, please contact your infineon counterpart to calculate the specific lifetime wit hin your application. table 45 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime t op cc ?? table 46 and table 47 esd susceptibility according to human body model (hbm) v hbm sr ?? ?? ? table 46 typical usage temperature profile operating time (sum = 20 years) operating temperat. notes 1 200 h t j = 150c normal operation 3 600 h t j = 125c normal operation 7 200 h t j = 110c normal operation 12 000 h t j = 100c normal operation 7 t j = 0 table 47 long time storage temperature profile operating time (sum = 20 years) operating temperat. notes 2 000 h t j = 150c normal operation 16 000 h t j = 125c normal operation 6 000 h t j = 110c normal operation 151 200 h t j www.infineon.com published by infineon technologies ag |
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